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Commit a941795a authored by Robert Bragg's avatar Robert Bragg Committed by Daniel Vetter
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drm/i915: rename OACONTROL GEN7_OACONTROL 



OACONTROL changes quite a bit for gen8, with some bits split out into a
per-context OACTXCONTROL register. Rename now before adding more gen7 OA
registers

Signed-off-by: default avatarRobert Bragg <robert@sixbynine.org>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Reviewed-by: default avatarSourab Gupta <sourab.gupta@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-3-robert@sixbynine.org
parent eec688e1

drivers/gpu/drm/i915/gvt/handlers.c

+1 −1
Original line number Diff line number Diff line
@@ -2200,7 +2200,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);



	MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL);

	MMIO_D(OACONTROL, D_HSW);

	MMIO_D(GEN7_OACONTROL, D_HSW);

	MMIO_D(0x2b00, D_BDW_PLUS);

	MMIO_D(0x2360, D_BDW_PLUS);

	MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/i915_cmd_parser.c

+2 −2
Original line number Diff line number Diff line
@@ -450,7 +450,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 
	REG64(PS_INVOCATION_COUNT),

	REG64(PS_DEPTH_COUNT),

	REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),

	REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */

	REG32(GEN7_OACONTROL), /* Only allowed for LRI and SRM. See below. */

	REG64(MI_PREDICATE_SRC0),

	REG64(MI_PREDICATE_SRC1),

	REG32(GEN7_3DPRIM_END_OFFSET),
@@ -1108,7 +1108,7 @@ static bool check_cmd(const struct intel_engine_cs *engine, 
			 * to the register. Hence, limit OACONTROL writes to

			 * only MI_LOAD_REGISTER_IMM commands.

			 */

			if (reg_addr == i915_mmio_reg_offset(OACONTROL)) {

			if (reg_addr == i915_mmio_reg_offset(GEN7_OACONTROL)) {

				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {

					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");

					return false;

drivers/gpu/drm/i915/i915_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -615,7 +615,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)

#define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)



#define OACONTROL _MMIO(0x2360)

#define GEN7_OACONTROL _MMIO(0x2360)



#define _GEN7_PIPEA_DE_LOAD_SL	0x70068

#define _GEN7_PIPEB_DE_LOAD_SL	0x71068