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Commit a8ed87c9 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
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powerpc/mm/radix: Add MMU_FTR_RADIX



We are going to add asm changes in the follow up patches. Add the
feature bit now so that we can get it all build.

mpe: When CONFIG_PPC_RADIX_MMU=n we omit MMU_FTR_RADIX from the
MMU_FTRS_POSSIBLE mask. This allows the compiler to work out that those
checks will always be false and so the code can be elided completely.

Note we do *not* define MMU_FTR_RADIX to 0 in the RADIX_MMU=n case,
because that doesn't work with the ASM_FTR patching. In particular an
IF_SET section will result in a mask and value of zero, which is always
true, meaning the section *won't* be patched, which is the opposite of
what we want.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: default avatarBalbir Singh <bsingharora@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 773edead
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+2 −1
Original line number Diff line number Diff line
@@ -23,7 +23,8 @@ struct mmu_psize_def {
};
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];

#define radix_enabled() (0)
#define radix_enabled() mmu_has_feature(MMU_FTR_RADIX)

#endif /* __ASSEMBLY__ */

/* 64-bit classic hash table MMU */
+10 −1
Original line number Diff line number Diff line
@@ -88,6 +88,11 @@
 */
#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)

/*
 * Radix page table available
 */
#define MMU_FTR_RADIX			ASM_CONST(0x80000000)

/* MMU feature bit sets for various CPUs */
#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\
	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
@@ -119,7 +124,11 @@ enum {
		MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
		MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
		MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
		MMU_FTR_1T_SEGMENT,
		MMU_FTR_1T_SEGMENT |
#ifdef CONFIG_PPC_RADIX_MMU
		MMU_FTR_RADIX |
#endif
		0,
};

static inline int mmu_has_feature(unsigned long feature)