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Commit a8b9234b authored by Henry Orosco's avatar Henry Orosco Committed by Jason Gunthorpe
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i40iw: Refactor of driver generated AEs



The flush CQP OP can be used to optionally generate
Asynchronous Events (AEs) in addition to QP flush.
Consolidate all HW AE generation code under a new
function i40iw_gen_ae which use the flush CQP OP
to only generate AEs.

Signed-off-by: default avatarHenry Orosco <henry.orosco@intel.com>
Signed-off-by: default avatarShiraz Saleem <shiraz.saleem@intel.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent 7f86260b
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+5 −0
Original line number Diff line number Diff line
@@ -572,6 +572,11 @@ enum i40iw_status_code i40iw_hw_flush_wqes(struct i40iw_device *iwdev,
					   struct i40iw_qp_flush_info *info,
					   bool wait);

void i40iw_gen_ae(struct i40iw_device *iwdev,
		  struct i40iw_sc_qp *qp,
		  struct i40iw_gen_ae_info *info,
		  bool wait);

void i40iw_copy_ip_ntohl(u32 *dst, __be32 *src);
struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *ib_pd,
				u64 addr,
+52 −4
Original line number Diff line number Diff line
@@ -2614,10 +2614,8 @@ static enum i40iw_status_code i40iw_sc_qp_flush_wqes(

	qp->flush_sq |= flush_sq;
	qp->flush_rq |= flush_rq;
	if (!flush_sq && !flush_rq) {
		if (info->ae_code != I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR)
	if (!flush_sq && !flush_rq)
		return 0;
	}

	cqp = qp->pd->dev->cqp;
	wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
@@ -2658,6 +2656,49 @@ static enum i40iw_status_code i40iw_sc_qp_flush_wqes(
	return 0;
}

/**
 * i40iw_sc_gen_ae - generate AE, currently uses flush WQE CQP OP
 * @qp: sc qp
 * @info: gen ae information
 * @scratch: u64 saved to be used during cqp completion
 * @post_sq: flag for cqp db to ring
 */
static enum i40iw_status_code i40iw_sc_gen_ae(
				struct i40iw_sc_qp *qp,
				struct i40iw_gen_ae_info *info,
				u64 scratch,
				bool post_sq)
{
	u64 temp;
	u64 *wqe;
	struct i40iw_sc_cqp *cqp;
	u64 header;

	cqp = qp->pd->dev->cqp;
	wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
	if (!wqe)
		return I40IW_ERR_RING_FULL;

	temp = info->ae_code |
	       LS_64(info->ae_source, I40IW_CQPSQ_FWQE_AESOURCE);

	set_64bit_val(wqe, 8, temp);

	header = qp->qp_uk.qp_id |
		 LS_64(I40IW_CQP_OP_GEN_AE, I40IW_CQPSQ_OPCODE) |
		 LS_64(1, I40IW_CQPSQ_FWQE_GENERATE_AE) |
		 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);

	i40iw_insert_wqe_hdr(wqe, header);

	i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "GEN_AE WQE",
			wqe, I40IW_CQP_WQE_SIZE * 8);

	if (post_sq)
		i40iw_sc_cqp_post_sq(cqp);
	return 0;
}

/**
 * i40iw_sc_qp_upload_context - upload qp's context
 * @dev: sc device struct
@@ -4148,6 +4189,13 @@ static enum i40iw_status_code i40iw_exec_cqp_cmd(struct i40iw_sc_dev *dev,
				pcmdinfo->in.u.qp_flush_wqes.
				scratch, pcmdinfo->post_sq);
		break;
	case OP_GEN_AE:
		status = i40iw_sc_gen_ae(
				pcmdinfo->in.u.gen_ae.qp,
				&pcmdinfo->in.u.gen_ae.info,
				pcmdinfo->in.u.gen_ae.scratch,
				pcmdinfo->post_sq);
		break;
	case OP_ADD_ARP_CACHE_ENTRY:
		status = i40iw_sc_add_arp_cache_entry(
				pcmdinfo->in.u.add_arp_cache_entry.cqp,
+4 −1
Original line number Diff line number Diff line
@@ -418,6 +418,8 @@
#define I40IW_CQP_OP_QUERY_FPM_VALUES           0x20
#define I40IW_CQP_OP_COMMIT_FPM_VALUES          0x21
#define I40IW_CQP_OP_FLUSH_WQES                 0x22
/* I40IW_CQP_OP_GEN_AE is the same value as I40IW_CQP_OP_FLUSH_WQES */
#define I40IW_CQP_OP_GEN_AE                     0x22
#define I40IW_CQP_OP_MANAGE_APBVT               0x23
#define I40IW_CQP_OP_NOP                        0x24
#define I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25
@@ -1729,6 +1731,7 @@ enum i40iw_alignment {
#define OP_COMMIT_FPM_VALUES                    30
#define OP_REQUESTED_COMMANDS                   31
#define OP_COMPLETED_COMMANDS                   32
#define OP_SIZE_CQP_STAT_ARRAY                  33
#define OP_GEN_AE                               33
#define OP_SIZE_CQP_STAT_ARRAY                  34

#endif
+33 −0
Original line number Diff line number Diff line
@@ -667,6 +667,39 @@ enum i40iw_status_code i40iw_hw_flush_wqes(struct i40iw_device *iwdev,
	return 0;
}

/**
 * i40iw_gen_ae - generate AE
 * @iwdev: iwarp device
 * @qp: qp associated with AE
 * @info: info for ae
 * @wait: wait for completion
 */
void i40iw_gen_ae(struct i40iw_device *iwdev,
		  struct i40iw_sc_qp *qp,
		  struct i40iw_gen_ae_info *info,
		  bool wait)
{
	struct i40iw_gen_ae_info *ae_info;
	struct i40iw_cqp_request *cqp_request;
	struct cqp_commands_info *cqp_info;

	cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
	if (!cqp_request)
		return;

	cqp_info = &cqp_request->info;
	ae_info = &cqp_request->info.in.u.gen_ae.info;
	memcpy(ae_info, info, sizeof(*ae_info));

	cqp_info->cqp_cmd = OP_GEN_AE;
	cqp_info->post_sq = 1;
	cqp_info->in.u.gen_ae.qp = qp;
	cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request;
	if (i40iw_handle_cqp_op(iwdev, cqp_request))
		i40iw_pr_err("CQP OP failed attempting to generate ae_code=0x%x\n",
			     info->ae_code);
}

/**
 * i40iw_hw_manage_vf_pble_bp - manage vf pbles
 * @iwdev: iwarp device
+11 −0
Original line number Diff line number Diff line
@@ -1004,6 +1004,11 @@ struct i40iw_cqp_query_fpm_values {
	u32 pbl_max;
};

struct i40iw_gen_ae_info {
	u16 ae_code;
	u8 ae_source;
};

struct i40iw_cqp_ops {
	enum i40iw_status_code (*cqp_init)(struct i40iw_sc_cqp *,
					   struct i40iw_cqp_init_info *);
@@ -1290,6 +1295,12 @@ struct cqp_info {
			u64 scratch;
		} qp_flush_wqes;

		struct {
			struct i40iw_sc_qp *qp;
			struct i40iw_gen_ae_info info;
			u64 scratch;
		} gen_ae;

		struct {
			struct i40iw_sc_cqp *cqp;
			void *fpm_values_va;
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