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Commit a8ab5ed5 authored by Tim Gore's avatar Tim Gore Committed by Tvrtko Ursulin
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drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate 



This patch enables a workaround for a mid thread preemption
issue where a hardware timing problem can prevent the
context restore from happening, leading to a hang.

v2: move to gen9_init_workarounds (Arun)
v3: move to start of gen9_init_workarounds (Arun)

Signed-off-by: default avatarTim Gore <tim.gore@intel.com>
Reviewed-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465816501-25557-1-git-send-email-tim.gore@intel.com
parent b50a5371

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -1810,6 +1810,10 @@ enum skl_disp_power_wells { 
#define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))

#define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))

#define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))

#define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))





/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */

#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)

#define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)



/* WaClearTdlStateAckDirtyBits */

/* WaClearTdlStateAckDirtyBits */

#define GEN8_STATE_ACK		_MMIO(0x20F0)

#define GEN8_STATE_ACK		_MMIO(0x20F0)

#define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)

#define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)

drivers/gpu/drm/i915/intel_ringbuffer.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -910,6 +910,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) 
	struct drm_i915_private *dev_priv = engine->i915;

	struct drm_i915_private *dev_priv = engine->i915;

	int ret;

	int ret;





	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */

	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));



	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */

	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */

	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |

	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |

		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);

		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);