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Commit a7ca2a70 authored by Marcel Ziswiler's avatar Marcel Ziswiler Committed by Thierry Reding
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dt-bindings: phy: Clarify ULPI PHY source clock 



cdev2 is not actually a clock on Tegra20 but rather a pinmux pad group.
PLL_P_OUT4 is the source clock for the ULPI PHY and is output to the
DAP_MCLK2 pad.

Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: default avatarDmitry Osipenko <digetx@gmail.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent ff0286cb

Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt

+3 −1
Original line number Diff line number Diff line
@@ -21,7 +21,9 @@ Required properties : 
   - timer: The timeout clock (clk_m). Present if phy_type == utmi.

   - utmi-pads: The clock needed to access the UTMI pad control registers.

     Present if phy_type == utmi.

   - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).

   - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2

     with pad group aka "nvidia,pins" cdev2 and pin mux option config aka

     "nvidia,function" pllp_out4).

     Present if phy_type == ulpi, and ULPI link mode is in use.

 - resets : Must contain an entry for each entry in reset-names.

   See ../reset/reset.txt for details.