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Commit a7a6c498 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: POSTING_READ() in intel_set_memory_cxsr() 



We want cxsr exit to happen ASAP, so toss in some POSTING_READ()s to
make sure things are really kicked off.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarClint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 031b698a

drivers/gpu/drm/i915/intel_pm.c

+5 −0
Original line number Diff line number Diff line
@@ -334,22 +334,27 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) 


	if (IS_VALLEYVIEW(dev)) {

		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);

		POSTING_READ(FW_BLC_SELF_VLV);

		if (IS_CHERRYVIEW(dev))

			chv_set_memory_pm5(dev_priv, enable);

	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {

		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);

		POSTING_READ(FW_BLC_SELF);

	} else if (IS_PINEVIEW(dev)) {

		val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;

		val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;

		I915_WRITE(DSPFW3, val);

		POSTING_READ(DSPFW3);

	} else if (IS_I945G(dev) || IS_I945GM(dev)) {

		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :

			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);

		I915_WRITE(FW_BLC_SELF, val);

		POSTING_READ(FW_BLC_SELF);

	} else if (IS_I915GM(dev)) {

		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :

			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);

		I915_WRITE(INSTPM, val);

		POSTING_READ(INSTPM);

	} else {

		return;

	}