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Commit a795e4e9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.0' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

misc radeon fixes.

* 'drm-fixes-4.0' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: only enable DP audio if the monitor supports it
  drm/radeon: fix atom aux payload size check for writes (v2)
  drm/radeon: fix 1 RB harvest config setup for TN/RL
  drm/radeon: enable SRBM timeout interrupt on EG/NI
  drm/radeon: enable SRBM timeout interrupt on SI
  drm/radeon: enable SRBM timeout interrupt on CIK v2
  drm/radeon: dump full IB if we hit a packet error
  drm/radeon: disable mclk switching with 120hz+ monitors
  drm/radeon: use drm_mode_vrefresh() rather than mode->vrefresh
  drm/radeon: enable native backlight control on old macs
parents 5b49afd6 3473f542

drivers/gpu/drm/radeon/atombios_dp.c

+7 −0
Original line number Diff line number Diff line
@@ -178,6 +178,13 @@ radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 
	switch (msg->request & ~DP_AUX_I2C_MOT) {

	case DP_AUX_NATIVE_WRITE:

	case DP_AUX_I2C_WRITE:

		/* The atom implementation only supports writes with a max payload of

		 * 12 bytes since it uses 4 bits for the total count (header + payload)

		 * in the parameter space.  The atom interface supports 16 byte

		 * payloads for reads. The hw itself supports up to 16 bytes of payload.

		 */

		if (WARN_ON_ONCE(msg->size > 12))

			return -E2BIG;

		/* tx_size needs to be 4 even for bare address packets since the atom

		 * table needs the info in tx_buf[3].

		 */

drivers/gpu/drm/radeon/atombios_encoders.c

+15 −6
Original line number Diff line number Diff line
@@ -731,7 +731,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) 
		dig_connector = radeon_connector->con_priv;

		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||

		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {

			if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))

			if (radeon_audio != 0 &&

			    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&

			    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))

				return ATOM_ENCODER_MODE_DP_AUDIO;

			return ATOM_ENCODER_MODE_DP;

		} else if (radeon_audio != 0) {
@@ -747,7 +749,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) 
		}

		break;

	case DRM_MODE_CONNECTOR_eDP:

		if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))

		if (radeon_audio != 0 &&

		    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&

		    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))

			return ATOM_ENCODER_MODE_DP_AUDIO;

		return ATOM_ENCODER_MODE_DP;

	case DRM_MODE_CONNECTOR_DVIA:
@@ -1720,8 +1724,10 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 
	}



	encoder_mode = atombios_get_encoder_mode(encoder);

	if (radeon_audio != 0 &&

		(encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))

	if (connector && (radeon_audio != 0) &&

	    ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||

	     (ENCODER_MODE_IS_DP(encoder_mode) &&

	      drm_detect_monitor_audio(radeon_connector_edid(connector)))))

		radeon_audio_dpms(encoder, mode);

}
@@ -2136,6 +2142,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 
	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

	int encoder_mode;



	radeon_encoder->pixel_clock = adjusted_mode->clock;
@@ -2164,8 +2171,10 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 
	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

		/* handled in dpms */

		encoder_mode = atombios_get_encoder_mode(encoder);

		if (radeon_audio != 0 &&

			(encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))

		if (connector && (radeon_audio != 0) &&

		    ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||

		     (ENCODER_MODE_IS_DP(encoder_mode) &&

		      drm_detect_monitor_audio(radeon_connector_edid(connector)))))

			radeon_audio_mode_set(encoder, adjusted_mode);

		break;

	case ENCODER_OBJECT_ID_INTERNAL_DDI:

drivers/gpu/drm/radeon/cik.c

+8 −0
Original line number Diff line number Diff line
@@ -3613,6 +3613,8 @@ static void cik_gpu_init(struct radeon_device *rdev) 
	}



	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));

	WREG32(SRBM_INT_CNTL, 0x1);

	WREG32(SRBM_INT_ACK, 0x1);



	WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
@@ -7230,6 +7232,8 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev) 
	WREG32(CP_ME2_PIPE3_INT_CNTL, 0);

	/* grbm */

	WREG32(GRBM_INT_CNTL, 0);

	/* SRBM */

	WREG32(SRBM_INT_CNTL, 0);

	/* vline/vblank, etc. */

	WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

	WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -8046,6 +8050,10 @@ int cik_irq_process(struct radeon_device *rdev) 
				break;

			}

			break;

		case 96:

			DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));

			WREG32(SRBM_INT_ACK, 0x1);

			break;

		case 124: /* UVD */

			DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);

			radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);

drivers/gpu/drm/radeon/cikd.h

+4 −0
Original line number Diff line number Diff line
@@ -482,6 +482,10 @@ 
#define		SOFT_RESET_ORB				(1 << 23)

#define		SOFT_RESET_VCE				(1 << 24)



#define SRBM_READ_ERROR					0xE98

#define SRBM_INT_CNTL					0xEA0

#define SRBM_INT_ACK					0xEA8



#define VM_L2_CNTL					0x1400

#define		ENABLE_L2_CACHE					(1 << 0)

#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)

drivers/gpu/drm/radeon/evergreen.c

+7 −0
Original line number Diff line number Diff line
@@ -3253,6 +3253,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	}



	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));

	WREG32(SRBM_INT_CNTL, 0x1);

	WREG32(SRBM_INT_ACK, 0x1);



	evergreen_fix_pci_max_read_req_size(rdev);
@@ -4324,6 +4326,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) 
	tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;

	WREG32(DMA_CNTL, tmp);

	WREG32(GRBM_INT_CNTL, 0);

	WREG32(SRBM_INT_CNTL, 0);

	WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

	WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

	if (rdev->num_crtc >= 4) {
@@ -5066,6 +5069,10 @@ int evergreen_irq_process(struct radeon_device *rdev) 
				DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);

				break;

			}

		case 96:

			DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));

			WREG32(SRBM_INT_ACK, 0x1);

			break;

		case 124: /* UVD */

			DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);

			radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);