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Commit a73fef10 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by David S. Miller
Browse files

net: mvpp2: rework RXQ interrupt group initialization for PPv2.2 



This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6763ce31

drivers/net/ethernet/marvell/mvpp2.c

+42 −4
Original line number Diff line number Diff line
@@ -185,7 +185,21 @@ 
/* Interrupt Cause and Mask registers */

#define MVPP2_ISR_RX_THRESHOLD_REG(rxq)		(0x5200 + 4 * (rxq))

#define     MVPP2_MAX_ISR_RX_THRESHOLD		0xfffff0

#define MVPP2_ISR_RXQ_GROUP_REG(rxq)		(0x5400 + 4 * (rxq))

#define MVPP21_ISR_RXQ_GROUP_REG(rxq)		(0x5400 + 4 * (rxq))



#define MVPP22_ISR_RXQ_GROUP_INDEX_REG          0x5400

#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf

#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380

#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7



#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf

#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380



#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG     0x5404

#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK    0x1f

#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK      0xf00

#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET    8



#define MVPP2_ISR_ENABLE_REG(port)		(0x5420 + 4 * (port))

#define     MVPP2_ISR_ENABLE_INTERRUPT(mask)	((mask) & 0xffff)

#define     MVPP2_ISR_DISABLE_INTERRUPT(mask)	(((mask) << 16) & 0xffff0000)
@@ -6406,7 +6420,18 @@ static int mvpp2_port_init(struct mvpp2_port *port) 
	}



	/* Configure Rx queue group interrupt for this port */

	mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), rxq_number);

	if (priv->hw_version == MVPP21) {

		mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),

			    rxq_number);

	} else {

		u32 val;



		val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);

		mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);



		val = (rxq_number << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);

		mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);

	}



	/* Create Rx descriptor rings */

	for (queue = 0; queue < rxq_number; queue++) {
@@ -6799,8 +6824,21 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 
	mvpp2_rx_fifo_init(priv);



	/* Reset Rx queue group interrupt configuration */

	for (i = 0; i < MVPP2_MAX_PORTS; i++)

		mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i), rxq_number);

	for (i = 0; i < MVPP2_MAX_PORTS; i++) {

		if (priv->hw_version == MVPP21) {

			mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),

				    rxq_number);

			continue;

		} else {

			u32 val;



			val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);

			mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);



			val = (rxq_number << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);

			mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);

		}

	}



	if (priv->hw_version == MVPP21)

		writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,