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Commit a68d68ee authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Add ILK/SNB/IVB WM latency field support 



Add a new function  ilk_wm_lp_latency() which will tell us what to write
into the WM_LPx register latency field. HSW is different from erlier
gens in this regard.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ac9545fd

drivers/gpu/drm/i915/intel_pm.c

+12 −1
Original line number Diff line number Diff line
@@ -2715,6 +2715,17 @@ static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) 
	return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);

}



/* The value we need to program into the WM_LPx latency field */

static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (IS_HASWELL(dev))

		return 2 * level;

	else

		return dev_priv->wm.pri_latency[level];

}



static void hsw_compute_wm_results(struct drm_device *dev,

				   const struct intel_pipe_wm *merged,

				   enum intel_ddb_partitioning partitioning,
@@ -2737,7 +2748,7 @@ static void hsw_compute_wm_results(struct drm_device *dev, 
			break;



		results->wm_lp[wm_lp - 1] = WM3_LP_EN |

			((level * 2) << WM1_LP_LATENCY_SHIFT) |

			(ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |

			(r->pri_val << WM1_LP_SR_SHIFT) |

			r->cur_val;