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Commit a644b277 authored Mar 03, 2009 by Shinya Kuribayashi Committed by Ralf Baechle Mar 11, 2009

MIPS: NEC VR5500 processor support fixup



Current VR5500 processor support lacks of some functions which are
expected to be configured/synthesized on arch initialization.

Here're some VR5500A spec notes:

* All execution hazards are handled in hardware.

* Once VR5500A stops the operation of the pipeline by WAIT instruction,
  it could return from the standby mode only when either a reset, NMI
  request, or all enabled interrupts is/are detected.  In other words,
  if interrupts are disabled by Status.IE=0, it keeps in standby mode
  even when interrupts are internally asserted.

  Notes on WAIT: The operation of the processor is undefined if WAIT
  insn is in the branch delay slot.  The operation is also undefined
  if WAIT insn is executed when Status.EXL and Status.ERL are set to 1.

* VR5500A core only implements the Load prefetch.

With these changes, it boots fine.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent c189846e

arch/mips/include/asm/hazards.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -138,7 +138,8 @@ do { \
		__instruction_hazard(); \
		} while (0)

		#elif defined(CONFIG_CPU_R10000) \|\| defined(CONFIG_CPU_CAVIUM_OCTEON)
		#elif defined(CONFIG_CPU_R10000) \|\| defined(CONFIG_CPU_CAVIUM_OCTEON) \|\| \
		defined(CONFIG_CPU_R5500)

		/*
		* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.

arch/mips/include/asm/prefetch.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -26,7 +26,7 @@
		* Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
		* current versions due to erratum G105.
		*
		* VR7701 only implements the Load prefetch.
		* VR5500 (including VR5701 and VR7701) only implement load prefetch.
		*
		* Finally MIPS32 and MIPS64 implement all of the following hints.
		*/

arch/mips/kernel/cpu-probe.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -149,6 +149,7 @@ void __init check_wait(void)
		case CPU_R4650:
		case CPU_R4700:
		case CPU_R5000:
		case CPU_R5500:
		case CPU_NEVADA:
		case CPU_4KC:
		case CPU_4KEC:

arch/mips/mm/page.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void)
		*/
		cache_line_size = cpu_dcache_line_size();
		switch (current_cpu_type()) {
		case CPU_R5500:
		case CPU_TX49XX:
		/* TX49 supports only Pref_Load */
		/* These processors only support the Pref_Load. */
		pref_bias_copy_load = 256;
		break;

arch/mips/mm/tlbex.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 p, struct uasm_label l,
		case CPU_BCM4710:
		case CPU_LOONGSON2:
		case CPU_CAVIUM_OCTEON:
		case CPU_R5500:
		if (m4kc_tlbp_war())
		uasm_i_nop(p);
		tlbw(p);