Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a6089879 authored by Tarun Vyas's avatar Tarun Vyas Committed by Dhinakaran Pandiyan
Browse files

drm/i915: Wait for PSR exit before checking for vblank evasion 



The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
the pipe_update_start call schedules itself out to check back later.

On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
lags w.r.t core kernel code, hot plugging an external display triggers
tons of "potential atomic update errors" in the dmesg, on *pipe A*. A
closer analysis reveals that we try to read the scanline 3 times and
eventually timeout, b/c PSR hasn't exited fully leading to a PIPEDSL
stuck @ 1599. This issue is not seen on upstream kernels, b/c for *some*
reason we loop inside intel_pipe_update start for ~2+ msec which in this
case is more than enough to exit PSR fully, hence an *unstuck* PIPEDSL
counter, hence no error. On the other hand, the ChromeOS kernel spends
~1.1 msec looping inside intel_pipe_update_start and hence errors out
b/c the source is still in PSR.

Regardless, we should wait for PSR exit (if PSR is disabled, we incur
a ~1-2 usec penalty) before reading the PIPEDSL, b/c if we haven't
fully exited PSR, then checking for vblank evasion isn't actually
applicable.

v4: Comment explaining psr_wait after enabling VBL interrupts (DK)

v5: CAN_PSR() to handle platforms that don't support PSR.

v6: Handle local_irq_disable on early return (Chris)

Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: default avatarTarun Vyas <tarun.vyas@intel.com>
Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180627200250.1515-2-tarun.vyas@intel.com
parent c43dbcbb

drivers/gpu/drm/i915/intel_sprite.c

+16 −4
Original line number Diff line number Diff line
@@ -107,13 +107,21 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) 
						      VBLANK_EVASION_TIME_US);

	max = vblank_start - 1;



	local_irq_disable();



	if (min <= 0 || max <= 0)

		return;

		goto irq_disable;



	if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))

		return;

		goto irq_disable;



	/*

	 * Wait for psr to idle out after enabling the VBL interrupts

	 * VBL interrupts will start the PSR exit and prevent a PSR

	 * re-entry as well.

	 */

	if (CAN_PSR(dev_priv) && intel_psr_wait_for_idle(dev_priv))

		DRM_ERROR("PSR idle timed out, atomic update may fail\n");



	local_irq_disable();



	crtc->debug.min_vbl = min;

	crtc->debug.max_vbl = max;
@@ -171,6 +179,10 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) 
	crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);



	trace_i915_pipe_update_vblank_evaded(crtc);

	return;



irq_disable:

	local_irq_disable();

}



/**