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Commit a58997e1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes-4.2' of git://people.freedesktop.org/~agd5f/linux 

Pull amdgpu fixes from Alex Deucher:
 "Just a few amdgpu fixes to make sure we report the proper firmware
  information and number of render buffers to userspace and a typo in a
  debugging function"

[ Pulling directly from Alex since Dave Airlie is on vacation  - Linus ]

* 'drm-fixes-4.2' of git://people.freedesktop.org/~agd5f/linux:
  drm/amdgpu: set fw_version and feature_version for smu fw loading
  drm/amdgpu: add feature version for SDMA ucode
  drm/amdgpu: add feature version for RLC and MEC v2
  drm/amdgpu: increment queue when iterating on this variable.
  drm/amdgpu: fix rb setting for CZ
parents ebc90be6 595fd013

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -1130,6 +1130,9 @@ struct amdgpu_gfx { 
	uint32_t			me_feature_version;

	uint32_t			me_feature_version;

	uint32_t			ce_feature_version;

	uint32_t			ce_feature_version;

	uint32_t			pfp_feature_version;

	uint32_t			pfp_feature_version;

	uint32_t			rlc_feature_version;

	uint32_t			mec_feature_version;

	uint32_t			mec2_feature_version;

	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];

	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];

	unsigned			num_gfx_rings;

	unsigned			num_gfx_rings;

	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];

	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
@@ -1639,6 +1642,7 @@ struct amdgpu_sdma { 
	/* SDMA firmware */

	/* SDMA firmware */

	const struct firmware	*fw;

	const struct firmware	*fw;

	uint32_t		fw_version;

	uint32_t		fw_version;

	uint32_t		feature_version;





	struct amdgpu_ring	ring;

	struct amdgpu_ring	ring;

};

};

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+7 −6
Original line number Original line Diff line number Diff line
@@ -317,16 +317,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
			break;

			break;

		case AMDGPU_INFO_FW_GFX_RLC:

		case AMDGPU_INFO_FW_GFX_RLC:

			fw_info.ver = adev->gfx.rlc_fw_version;

			fw_info.ver = adev->gfx.rlc_fw_version;

			fw_info.feature = 0;

			fw_info.feature = adev->gfx.rlc_feature_version;

			break;

			break;

		case AMDGPU_INFO_FW_GFX_MEC:

		case AMDGPU_INFO_FW_GFX_MEC:

			if (info->query_fw.index == 0)

			if (info->query_fw.index == 0) {

				fw_info.ver = adev->gfx.mec_fw_version;

				fw_info.ver = adev->gfx.mec_fw_version;

			else if (info->query_fw.index == 1)

				fw_info.feature = adev->gfx.mec_feature_version;

			} else if (info->query_fw.index == 1) {

				fw_info.ver = adev->gfx.mec2_fw_version;

				fw_info.ver = adev->gfx.mec2_fw_version;

			else

				fw_info.feature = adev->gfx.mec2_feature_version;

			} else

				return -EINVAL;

				return -EINVAL;

			fw_info.feature = 0;

			break;

			break;

		case AMDGPU_INFO_FW_SMC:

		case AMDGPU_INFO_FW_SMC:

			fw_info.ver = adev->pm.fw_version;

			fw_info.ver = adev->pm.fw_version;
@@ -336,7 +337,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
			if (info->query_fw.index >= 2)

			if (info->query_fw.index >= 2)

				return -EINVAL;

				return -EINVAL;

			fw_info.ver = adev->sdma[info->query_fw.index].fw_version;

			fw_info.ver = adev->sdma[info->query_fw.index].fw_version;

			fw_info.feature = 0;

			fw_info.feature = adev->sdma[info->query_fw.index].feature_version;

			break;

			break;

		default:

		default:

			return -EINVAL;

			return -EINVAL;

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -500,6 +500,7 @@ static int cik_sdma_load_microcode(struct amdgpu_device *adev) 
		amdgpu_ucode_print_sdma_hdr(&hdr->header);

		amdgpu_ucode_print_sdma_hdr(&hdr->header);

		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;

		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;

		adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);

		adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);

		adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);

		fw_data = (const __le32 *)

		fw_data = (const __le32 *)

			(adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));

			(adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));

		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);

		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+7 −1
Original line number Original line Diff line number Diff line
@@ -3080,6 +3080,8 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 
	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;

	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;

	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);

	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);

	adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);

	adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);

	adev->gfx.mec_feature_version = le32_to_cpu(

					mec_hdr->ucode_feature_version);





	gfx_v7_0_cp_compute_enable(adev, false);

	gfx_v7_0_cp_compute_enable(adev, false);
@@ -3102,6 +3104,8 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 
		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;

		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;

		amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);

		amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);

		adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);

		adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);

		adev->gfx.mec2_feature_version = le32_to_cpu(

				mec2_hdr->ucode_feature_version);





		/* MEC2 */

		/* MEC2 */

		fw_data = (const __le32 *)

		fw_data = (const __le32 *)
@@ -4066,6 +4070,8 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 
	hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;

	hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;

	amdgpu_ucode_print_rlc_hdr(&hdr->header);

	amdgpu_ucode_print_rlc_hdr(&hdr->header);

	adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);

	adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);

	adev->gfx.rlc_feature_version = le32_to_cpu(

					hdr->ucode_feature_version);





	gfx_v7_0_rlc_stop(adev);

	gfx_v7_0_rlc_stop(adev);
@@ -5122,7 +5128,7 @@ static void gfx_v7_0_print_status(void *handle) 
		dev_info(adev->dev, "  CP_HPD_EOP_CONTROL=0x%08X\n",

		dev_info(adev->dev, "  CP_HPD_EOP_CONTROL=0x%08X\n",

			 RREG32(mmCP_HPD_EOP_CONTROL));

			 RREG32(mmCP_HPD_EOP_CONTROL));





		for (queue = 0; queue < 8; i++) {

		for (queue = 0; queue < 8; queue++) {

			cik_srbm_select(adev, me, pipe, queue, 0);

			cik_srbm_select(adev, me, pipe, queue, 0);

			dev_info(adev->dev, "  queue: %d\n", queue);

			dev_info(adev->dev, "  queue: %d\n", queue);

			dev_info(adev->dev, "  CP_PQ_WPTR_POLL_CNTL=0x%08X\n",

			dev_info(adev->dev, "  CP_PQ_WPTR_POLL_CNTL=0x%08X\n",

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+23 −13
Original line number Original line Diff line number Diff line
@@ -587,6 +587,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	int err;

	int err;

	struct amdgpu_firmware_info *info = NULL;

	struct amdgpu_firmware_info *info = NULL;

	const struct common_firmware_header *header = NULL;

	const struct common_firmware_header *header = NULL;

	const struct gfx_firmware_header_v1_0 *cp_hdr;





	DRM_DEBUG("\n");

	DRM_DEBUG("\n");
@@ -611,6 +612,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);

	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);

	if (err)

	if (err)

		goto out;

		goto out;

	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;

	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);





	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);

	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);

	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
@@ -619,6 +623,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	err = amdgpu_ucode_validate(adev->gfx.me_fw);

	err = amdgpu_ucode_validate(adev->gfx.me_fw);

	if (err)

	if (err)

		goto out;

		goto out;

	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;

	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);





	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);

	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);

	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
@@ -627,12 +634,18 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	err = amdgpu_ucode_validate(adev->gfx.ce_fw);

	err = amdgpu_ucode_validate(adev->gfx.ce_fw);

	if (err)

	if (err)

		goto out;

		goto out;

	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;

	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);





	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);

	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);

	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);

	if (err)

	if (err)

		goto out;

		goto out;

	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);

	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);

	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;

	adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);





	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);

	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);

	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
@@ -641,6 +654,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
	err = amdgpu_ucode_validate(adev->gfx.mec_fw);

	err = amdgpu_ucode_validate(adev->gfx.mec_fw);

	if (err)

	if (err)

		goto out;

		goto out;

	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;

	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);





	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);

	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);

	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
@@ -648,6 +664,12 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 
		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);

		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);

		if (err)

		if (err)

			goto out;

			goto out;

		cp_hdr = (const struct gfx_firmware_header_v1_0 *)

						adev->gfx.mec2_fw->data;

		adev->gfx.mec2_fw_version = le32_to_cpu(

						cp_hdr->header.ucode_version);

		adev->gfx.mec2_feature_version = le32_to_cpu(

						cp_hdr->ucode_feature_version);

	} else {

	} else {

		err = 0;

		err = 0;

		adev->gfx.mec2_fw = NULL;

		adev->gfx.mec2_fw = NULL;
@@ -1983,6 +2005,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) 
		adev->gfx.config.max_shader_engines = 1;

		adev->gfx.config.max_shader_engines = 1;

		adev->gfx.config.max_tile_pipes = 2;

		adev->gfx.config.max_tile_pipes = 2;

		adev->gfx.config.max_sh_per_se = 1;

		adev->gfx.config.max_sh_per_se = 1;

		adev->gfx.config.max_backends_per_se = 2;





		switch (adev->pdev->revision) {

		switch (adev->pdev->revision) {

		case 0xc4:

		case 0xc4:
@@ -1991,7 +2014,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) 
		case 0xcc:

		case 0xcc:

			/* B10 */

			/* B10 */

			adev->gfx.config.max_cu_per_sh = 8;

			adev->gfx.config.max_cu_per_sh = 8;

			adev->gfx.config.max_backends_per_se = 2;

			break;

			break;

		case 0xc5:

		case 0xc5:

		case 0x81:

		case 0x81:
@@ -2000,14 +2022,12 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) 
		case 0xcd:

		case 0xcd:

			/* B8 */

			/* B8 */

			adev->gfx.config.max_cu_per_sh = 6;

			adev->gfx.config.max_cu_per_sh = 6;

			adev->gfx.config.max_backends_per_se = 2;

			break;

			break;

		case 0xc6:

		case 0xc6:

		case 0xca:

		case 0xca:

		case 0xce:

		case 0xce:

			/* B6 */

			/* B6 */

			adev->gfx.config.max_cu_per_sh = 6;

			adev->gfx.config.max_cu_per_sh = 6;

			adev->gfx.config.max_backends_per_se = 2;

			break;

			break;

		case 0xc7:

		case 0xc7:

		case 0x87:

		case 0x87:
@@ -2015,7 +2035,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) 
		default:

		default:

			/* B4 */

			/* B4 */

			adev->gfx.config.max_cu_per_sh = 4;

			adev->gfx.config.max_cu_per_sh = 4;

			adev->gfx.config.max_backends_per_se = 1;

			break;

			break;

		}

		}
@@ -2275,7 +2294,6 @@ static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev) 




	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;

	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;

	amdgpu_ucode_print_rlc_hdr(&hdr->header);

	amdgpu_ucode_print_rlc_hdr(&hdr->header);

	adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);





	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +

	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +

			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));

			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
@@ -2361,12 +2379,6 @@ static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 
	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);

	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);

	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);

	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);

	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);

	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);

	adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);

	adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);

	adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);

	adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);

	adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);

	adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);





	gfx_v8_0_cp_gfx_enable(adev, false);

	gfx_v8_0_cp_gfx_enable(adev, false);
@@ -2622,7 +2634,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) 




	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;

	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;

	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);

	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);

	adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);





	fw_data = (const __le32 *)

	fw_data = (const __le32 *)

		(adev->gfx.mec_fw->data +

		(adev->gfx.mec_fw->data +
@@ -2641,7 +2652,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) 




		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;

		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;

		amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);

		amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);

		adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);





		fw_data = (const __le32 *)

		fw_data = (const __le32 *)

			(adev->gfx.mec2_fw->data +

			(adev->gfx.mec2_fw->data +