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Commit a4eff16c authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull parsic updates from Helge Deller:
 "This patchset includes two major fixes which are both scheduled for
  stable:

  First, __ARCH_SI_PREAMBLE_SIZE was defined with a wrong value.
  Second, huge page pte and TLB changes needed protection with a
  spinlock.  Other than that there are just some trivial optimizations
  and cleanups"

* 'parisc-4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: Protect huge page pte changes with spinlocks
  parisc: Imporove debug info about space registers and TLB configuration
  parisc: Drop parisc-specific NSIGTRAP define
  parisc: Fix __ARCH_SI_PREAMBLE_SIZE
  parisc: Reduce overhead of parisc_requires_coherency()
  parisc: Initialize PCI bridge cache line and default latency
parents 0cbeafb2 b0e55131
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+4 −16
Original line number Diff line number Diff line
@@ -54,24 +54,12 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
	return pte_wrprotect(pte);
}

static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
					   unsigned long addr, pte_t *ptep)
{
	pte_t old_pte = *ptep;
	set_huge_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
}
void huge_ptep_set_wrprotect(struct mm_struct *mm,
					   unsigned long addr, pte_t *ptep);

static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
int huge_ptep_set_access_flags(struct vm_area_struct *vma,
					     unsigned long addr, pte_t *ptep,
					     pte_t pte, int dirty)
{
	int changed = !pte_same(*ptep, pte);
	if (changed) {
		set_huge_pte_at(vma->vm_mm, addr, ptep, pte);
		flush_tlb_page(vma, addr);
	}
	return changed;
}
					     pte_t pte, int dirty);

static inline pte_t huge_ptep_get(pte_t *ptep)
{
+1 −0
Original line number Diff line number Diff line
@@ -167,6 +167,7 @@ static inline void pcibios_register_hba(struct pci_hba_data *x)
{
}
#endif
extern void pcibios_init_bridge(struct pci_dev *);

/*
 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
+1 −1
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ struct pdc_tlb_cf { /* for PDC_CACHE (I/D-TLB's) */
		tc_page : 1,	/* 0 = 2K page-size-machine, 1 = 4k page size */
		tc_cst  : 3,	/* 0 = incoherent operations, else coherent operations */
		tc_aid  : 5,	/* ITLB: width of access ids of processor (encoded!) */
		tc_pad1 : 8;	/* ITLB: width of space-registers (encoded) */
		tc_sr   : 8;	/* ITLB: width of space-registers (encoded) */
};

struct pdc_cache_info {		/* main-PDC_CACHE-structure (caches & TLB's) */
+8 −9
Original line number Diff line number Diff line
@@ -311,18 +311,17 @@ extern unsigned long get_wchan(struct task_struct *p);
#define cpu_relax()	barrier()
#define cpu_relax_lowlatency() cpu_relax()

/* Used as a macro to identify the combined VIPT/PIPT cached
 * CPUs which require a guarantee of coherency (no inequivalent
 * aliases with different data, whether clean or not) to operate */
static inline int parisc_requires_coherency(void)
{
/*
 * parisc_requires_coherency() is used to identify the combined VIPT/PIPT
 * cached CPUs which require a guarantee of coherency (no inequivalent aliases
 * with different data, whether clean or not) to operate
 */
#ifdef CONFIG_PA8X00
	return (boot_cpu_data.cpu_type == mako) ||
		(boot_cpu_data.cpu_type == mako2);
extern int _parisc_requires_coherency;
#define parisc_requires_coherency()	_parisc_requires_coherency
#else
	return 0;
#define parisc_requires_coherency()	(0)
#endif
}

#endif /* __ASSEMBLY__ */

+4 −3
Original line number Diff line number Diff line
#ifndef _PARISC_SIGINFO_H
#define _PARISC_SIGINFO_H

#include <asm-generic/siginfo.h>
#if defined(__LP64__)
#define __ARCH_SI_PREAMBLE_SIZE   (4 * sizeof(int))
#endif

#undef NSIGTRAP
#define NSIGTRAP	4
#include <asm-generic/siginfo.h>

#endif
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