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Commit a4632aae authored by Xiangliang Yu's avatar Xiangliang Yu Committed by James Bottomley
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[SCSI] mvsas: Add new macros and functions 



Add new macros: MVS_SOFT_RESET, MVS_HARD_RESET, MVS_PHY_TUNE,
	MVS_COMMAND_ACTIVE, EXP_BRCT_CHG, MVS_MAX_SG
Add new member sg_width in struct mvs_chip_info
Use macros rather than magic number
Add new functions: mvs_fill_ssp_resp_iu, mvs_set_sense,
	mvs_94xx_clear_srs_irq, mvs_94xx_phy_set_link_rate

Signed-off-by: default avatarXiangliang Yu <yuxiangl@marvell.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent b89e8f53

drivers/scsi/mvsas/mv_64xx.c

+9 −9
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ static void __devinit mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id) 
	u32 tmp;



	tmp = mr32(MVS_PCS);

	if (mvi->chip->n_phy <= 4)

	if (mvi->chip->n_phy <= MVS_SOC_PORTS)

		tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT);

	else

		tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
@@ -95,7 +95,7 @@ static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id) 
	u32 reg, tmp;



	if (!(mvi->flags & MVF_FLAG_SOC)) {

		if (phy_id < 4)

		if (phy_id < MVS_SOC_PORTS)

			pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &reg);

		else

			pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &reg);
@@ -104,13 +104,13 @@ static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id) 
		reg = mr32(MVS_PHY_CTL);



	tmp = reg;

	if (phy_id < 4)

	if (phy_id < MVS_SOC_PORTS)

		tmp |= (1U << phy_id) << PCTL_LINK_OFFS;

	else

		tmp |= (1U << (phy_id - 4)) << PCTL_LINK_OFFS;

		tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS;



	if (!(mvi->flags & MVF_FLAG_SOC)) {

		if (phy_id < 4) {

		if (phy_id < MVS_SOC_PORTS) {

			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);

			mdelay(10);

			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);
@@ -133,9 +133,9 @@ static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) 
	tmp &= ~PHYEV_RDY_CH;

	mvs_write_port_irq_stat(mvi, phy_id, tmp);

	tmp = mvs_read_phy_ctl(mvi, phy_id);

	if (hard == 1)

	if (hard == MVS_HARD_RESET)

		tmp |= PHY_RST_HARD;

	else if (hard == 0)

	else if (hard == MVS_SOFT_RESET)

		tmp |= PHY_RST;

	mvs_write_phy_ctl(mvi, phy_id, tmp);

	if (hard) {
@@ -346,7 +346,7 @@ static int __devinit mvs_64xx_init(struct mvs_info *mvi) 


		mvs_64xx_enable_xmt(mvi, i);



		mvs_64xx_phy_reset(mvi, i, 1);

		mvs_64xx_phy_reset(mvi, i, MVS_HARD_RESET);

		msleep(500);

		mvs_64xx_detect_porttype(mvi, i);

	}
@@ -661,7 +661,7 @@ void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, 
		tmp |= lrmax;

	}

	mvs_write_phy_ctl(mvi, phy_id, tmp);

	mvs_64xx_phy_reset(mvi, phy_id, 1);

	mvs_64xx_phy_reset(mvi, phy_id, MVS_HARD_RESET);

}



static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)

drivers/scsi/mvsas/mv_94xx.c

+59 −21
Original line number Diff line number Diff line
@@ -389,7 +389,7 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi) 
	mvs_phy_hacks(mvi);



	/* set LED blink when IO*/

	mw32(MVS_PA_VSR_ADDR, 0x00000030);

	mw32(MVS_PA_VSR_ADDR, VSR_PHY_ACT_LED);

	tmp = mr32(MVS_PA_VSR_PORT);

	tmp &= 0xFFFF00FF;

	tmp |= 0x00003300;
@@ -419,7 +419,7 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi) 
		mvs_94xx_config_reg_from_hba(mvi, i);

		mvs_94xx_phy_enable(mvi, i);



		mvs_94xx_phy_reset(mvi, i, 1);

		mvs_94xx_phy_reset(mvi, i, PHY_RST_HARD);

		msleep(500);

		mvs_94xx_detect_porttype(mvi, i);

	}
@@ -585,23 +585,59 @@ static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat) 
static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)

{

	u32 tmp;

	mvs_cw32(mvi, 0x300 + (slot_idx >> 3), 1 << (slot_idx % 32));

	tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3));

	if (tmp && 1 << (slot_idx % 32)) {

		mv_printk("command active %08X,  slot [%x].\n", tmp, slot_idx);

		mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3),

			1 << (slot_idx % 32));

		do {

		tmp = mvs_cr32(mvi, 0x300 + (slot_idx >> 3));

			tmp = mvs_cr32(mvi,

				MVS_COMMAND_ACTIVE + (slot_idx >> 3));

		} while (tmp & 1 << (slot_idx % 32));

	}

}



static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,

				u32 tfs)

void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)

{

	void __iomem *regs = mvi->regs;

	u32 tmp;



	if (type == PORT_TYPE_SATA) {

		tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);

	if (clear_all) {

		tmp = mr32(MVS_INT_STAT_SRS_0);

		if (tmp) {

			mv_dprintk("check SRS 0 %08X.\n", tmp);

			mw32(MVS_INT_STAT_SRS_0, tmp);

		}

	mw32(MVS_INT_STAT, CINT_CI_STOP);

		tmp = mr32(MVS_INT_STAT_SRS_1);

		if (tmp) {

			mv_dprintk("check SRS 1 %08X.\n", tmp);

			mw32(MVS_INT_STAT_SRS_1, tmp);

		}

	} else {

		if (reg_set > 31)

			tmp = mr32(MVS_INT_STAT_SRS_1);

		else

			tmp = mr32(MVS_INT_STAT_SRS_0);



		if (tmp & (1 << (reg_set % 32))) {

			mv_dprintk("register set 0x%x was stopped.\n", reg_set);

			if (reg_set > 31)

				mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32));

			else

				mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));

		}

	}

}



static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,

				u32 tfs)

{

	void __iomem *regs = mvi->regs;

	u32 tmp;

	mvs_94xx_clear_srs_irq(mvi, 0, 1);



	tmp = mr32(MVS_INT_STAT);

	mw32(MVS_INT_STAT, tmp | CINT_CI_STOP);

	tmp = mr32(MVS_PCS) | 0xFF00;

	mw32(MVS_PCS, tmp);

}
@@ -794,7 +830,18 @@ static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i, 
void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,

			struct sas_phy_linkrates *rates)

{

	/* TODO */

	u32 lrmax = 0;

	u32 tmp;



	tmp = mvs_read_phy_ctl(mvi, phy_id);

	lrmax = (rates->maximum_linkrate - SAS_LINK_RATE_1_5_GBPS) << 12;



	if (lrmax) {

		tmp &= ~(0x3 << 12);

		tmp |= lrmax;

	}

	mvs_write_phy_ctl(mvi, phy_id, tmp);

	mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD);

}



static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
@@ -893,15 +940,6 @@ void mvs_94xx_fix_dma(struct mvs_info *mvi, u32 phy_mask, 
	}

}



/*

 * FIXME JEJB: temporary nop clear_srs_irq to make 94xx still work

 * with 64xx fixes

 */

static void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set,

				   u8 clear_all)

{

}



static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time)

{

	void __iomem *regs = mvi->regs;

drivers/scsi/mvsas/mv_94xx.h

+2 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ enum hw_registers { 
	MVS_P4_VSR_DATA 	= 0x254, /* phy4 VSR data */

	MVS_PA_VSR_ADDR		= 0x290, /* All port VSR addr */

	MVS_PA_VSR_PORT		= 0x294, /* All port VSR data */

	MVS_COMMAND_ACTIVE	= 0x300,

};



enum pci_cfg_registers {
@@ -132,6 +133,7 @@ enum sas_sata_vsp_regs { 
	VSR_PHY_MODE9		= 0x09 * 4, /* Test */

	VSR_PHY_MODE10		= 0x0A * 4, /* Power */

	VSR_PHY_MODE11		= 0x0B * 4, /* Phy Mode */

	VSR_PHY_ACT_LED		= 0x0C * 4, /* Activity LED control */



	VSR_PHY_FFE_CONTROL	= 0x10C,

	VSR_PHY_DFE_UPDATE_CRTL	= 0x110,

drivers/scsi/mvsas/mv_defs.h

+2 −1
Original line number Diff line number Diff line
@@ -398,6 +398,7 @@ enum mvs_event_flags { 
	PHY_PLUG_EVENT		= (3U),

	PHY_PLUG_IN		= (1U << 0),	/* phy plug in */

	PHY_PLUG_OUT		= (1U << 1),	/* phy plug out */

	EXP_BRCT_CHG		= (1U << 2),	/* broadcast change */

};



enum mvs_port_type {

drivers/scsi/mvsas/mv_init.c

+11 −10
Original line number Diff line number Diff line
@@ -39,15 +39,15 @@ int interrupt_coalescing = 0x80; 
static struct scsi_transport_template *mvs_stt;

struct kmem_cache *mvs_task_list_cache;

static const struct mvs_chip_info mvs_chips[] = {

	[chip_6320] =	{ 1, 2, 0x400, 17, 16,  9, &mvs_64xx_dispatch, },

	[chip_6440] =	{ 1, 4, 0x400, 17, 16,  9, &mvs_64xx_dispatch, },

	[chip_6485] =	{ 1, 8, 0x800, 33, 32, 10, &mvs_64xx_dispatch, },

	[chip_9180] =	{ 2, 4, 0x800, 17, 64,  9, &mvs_94xx_dispatch, },

	[chip_9480] =	{ 2, 4, 0x800, 17, 64,  9, &mvs_94xx_dispatch, },

	[chip_9445] =	{ 1, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, },

	[chip_9485] =	{ 2, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, },

	[chip_1300] =	{ 1, 4, 0x400, 17, 16,  9, &mvs_64xx_dispatch, },

	[chip_1320] =	{ 2, 4, 0x800, 17, 64,  9, &mvs_94xx_dispatch, },

	[chip_6320] =	{ 1, 2, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },

	[chip_6440] =	{ 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },

	[chip_6485] =	{ 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },

	[chip_9180] =	{ 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },

	[chip_9480] =	{ 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },

	[chip_9445] =	{ 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },

	[chip_9485] =	{ 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },

	[chip_1300] =	{ 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },

	[chip_1320] =	{ 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },

};



struct device_attribute *mvst_host_attrs[];
@@ -466,7 +466,7 @@ static int __devinit mvs_prep_sas_ha_init(struct Scsi_Host *shost, 
	((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;



	shost->transportt = mvs_stt;

	shost->max_id = 128;

	shost->max_id = MVS_MAX_DEVICES;

	shost->max_lun = ~0;

	shost->max_channel = 1;

	shost->max_cmd_len = 16;
@@ -512,6 +512,7 @@ static void __devinit mvs_post_sas_ha_init(struct Scsi_Host *shost, 
		can_queue = MVS_CHIP_SLOT_SZ;



	sha->lldd_queue_size = can_queue;

	shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);

	shost->can_queue = can_queue;

	mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;

	sha->core.shost = mvi->shost;