Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a38ecbbd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Ingo Molnar:
 "A CR4-shadow 32-bit init fix, plus two typo fixes"

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86: Init per-cpu shadow copy of CR4 on 32-bit CPUs too
  x86/platform/intel-mid: Fix trivial printk message typo in intel_mid_arch_setup()
  x86/cpu/intel: Fix trivial typo in intel_tlb_table[]
parents 640c0f5c 5b2bdbc8

arch/x86/kernel/cpu/common.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -1396,6 +1396,12 @@ void cpu_init(void) 




	wait_for_master_cpu(cpu);

	wait_for_master_cpu(cpu);





	/*

	 * Initialize the CR4 shadow before doing anything that could

	 * try to read it.

	 */

	cr4_init_shadow();



	show_ucode_info_early();

	show_ucode_info_early();





	printk(KERN_INFO "Initializing CPU#%d\n", cpu);

	printk(KERN_INFO "Initializing CPU#%d\n", cpu);

arch/x86/kernel/cpu/intel.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -565,8 +565,8 @@ static const struct _tlb_table intel_tlb_table[] = { 
	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },

	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },

	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },

	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },

	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },

	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },

	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set ssociative" },

	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set associative" },

	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set ssociative" },

	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set associative" },

	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },

	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },

	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },

	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },

	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },

	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },

arch/x86/platform/intel-mid/intel-mid.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -130,7 +130,7 @@ static void intel_mid_arch_setup(void) 
		intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();

		intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();

	else {

	else {

		intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();

		intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();

		pr_info("ARCH: Uknown SoC, assuming PENWELL!\n");

		pr_info("ARCH: Unknown SoC, assuming PENWELL!\n");

	}

	}





out:

out: