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Commit a2f9663a authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge tag 'omap-for-v3.13/hwmod-signed' of... 

Merge tag 'omap-for-v3.13/hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

From Tony Lindgren:
omap hwmod related changes via Paul Walmsley <paul@pwsan.com>:

Some OMAP hwmod changes for 3.13.  Significant changes here include:

- support for moving some of the hwmod flags to DT data

- support for the SSI, hardware spinlock, USB host/TLL, and RNG IP
  blocks for various OMAPs

- a fix that again decouples hwmod data changes from unrelated DT data
  patchsets

Basic test logs are available at:

http://www.pwsan.com/omap/testlogs/prcm_fixes_v3.13/20131009094936/

* tag 'omap-for-v3.13/hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP5: hwmod: add missing ocp2scp hwmod data
  ARM: AM33xx: hwmod: Add RNG module data
  ARM: OMAP2+: hwmod: Extract no-idle and no-reset info from DT
  ARM: OMAP2+: hwmod: cleanup HWMOD_INIT_NO_RESET usage
  ARM: AM33xx: hwmod_data: add the sysc configuration for spinlock
  ARM: OMAP5: hwmod data: Add spinlock data
  ARM: OMAP5: hwmod data: Add USB Host and TLL modules
  ARM: OMAP2+: hwmod data: Add SSI information
  ARM: OMAP2+: hwmod: check for module address space during init
parents 8620d2c5 254f57a9

arch/arm/mach-omap2/omap_hwmod.c

+34 −15
Original line number Diff line number Diff line
@@ -2357,25 +2357,29 @@ static struct device_node *of_dev_hwmod_lookup(struct device_node *np, 
/**

 * _init_mpu_rt_base - populate the virtual address for a hwmod

 * @oh: struct omap_hwmod * to locate the virtual address

 * @data: (unused, caller should pass NULL)

 * @np: struct device_node * of the IP block's device node in the DT data

 *

 * Cache the virtual address used by the MPU to access this IP block's

 * registers.  This address is needed early so the OCP registers that

 * are part of the device's address space can be ioremapped properly.

 * No return value.

 *

 * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and

 * -ENXIO on absent or invalid register target address space.

 */

static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)

static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,

				    struct device_node *np)

{

	struct omap_hwmod_addr_space *mem;

	void __iomem *va_start = NULL;

	struct device_node *np;



	if (!oh)

		return;

		return -EINVAL;



	_save_mpu_port_index(oh);



	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)

		return;

		return -ENXIO;



	mem = _find_mpu_rt_addr_space(oh);

	if (!mem) {
@@ -2383,11 +2387,9 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) 
			 oh->name);



		/* Extract the IO space from device tree blob */

		if (!of_have_populated_dt())

			return;

		if (!np)

			return -ENXIO;



		np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);

		if (np)

		va_start = of_iomap(np, oh->mpu_rt_idx);

	} else {

		va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
@@ -2395,13 +2397,14 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) 


	if (!va_start) {

		pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);

		return;

		return -ENXIO;

	}



	pr_debug("omap_hwmod: %s: MPU register target at va %p\n",

		 oh->name, va_start);



	oh->_mpu_rt_va = va_start;

	return 0;

}



/**
@@ -2414,18 +2417,28 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) 
 * registered at this point.  This is the first of two phases for

 * hwmod initialization.  Code called here does not touch any hardware

 * registers, it simply prepares internal data structures.  Returns 0

 * upon success or if the hwmod isn't registered, or -EINVAL upon

 * failure.

 * upon success or if the hwmod isn't registered or if the hwmod's

 * address space is not defined, or -EINVAL upon failure.

 */

static int __init _init(struct omap_hwmod *oh, void *data)

{

	int r;

	struct device_node *np = NULL;



	if (oh->_state != _HWMOD_STATE_REGISTERED)

		return 0;



	if (oh->class->sysc)

		_init_mpu_rt_base(oh, NULL);

	if (of_have_populated_dt())

		np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);



	if (oh->class->sysc) {

		r = _init_mpu_rt_base(oh, NULL, np);

		if (r < 0) {

			WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",

			     oh->name);

			return 0;

		}

	}



	r = _init_clocks(oh, NULL);

	if (r < 0) {
@@ -2433,6 +2446,12 @@ static int __init _init(struct omap_hwmod *oh, void *data) 
		return -EINVAL;

	}



	if (np)

		if (of_find_property(np, "ti,no-reset-on-init", NULL))

			oh->flags |= HWMOD_INIT_NO_RESET;

		if (of_find_property(np, "ti,no-idle-on-init", NULL))

			oh->flags |= HWMOD_INIT_NO_IDLE;



	oh->_state = _HWMOD_STATE_INITIALIZED;



	return 0;

arch/arm/mach-omap2/omap_hwmod_33xx_data.c

+58 −9
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ static struct omap_hwmod am33xx_emif_hwmod = { 
	.name		= "emif",

	.class		= &am33xx_emif_hwmod_class,

	.clkdm_name	= "l3_clkdm",

	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "dpll_ddr_m2_div2_ck",

	.prcm		= {

		.omap4	= {
@@ -74,7 +74,7 @@ static struct omap_hwmod am33xx_l3_main_hwmod = { 
	.name		= "l3_main",

	.class		= &am33xx_l3_hwmod_class,

	.clkdm_name	= "l3_clkdm",

	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "l3_gclk",

	.prcm		= {

		.omap4	= {
@@ -96,7 +96,7 @@ static struct omap_hwmod am33xx_l3_instr_hwmod = { 
	.name		= "l3_instr",

	.class		= &am33xx_l3_hwmod_class,

	.clkdm_name	= "l3_clkdm",

	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "l3_gclk",

	.prcm		= {

		.omap4	= {
@@ -119,7 +119,7 @@ static struct omap_hwmod am33xx_l4_ls_hwmod = { 
	.name		= "l4_ls",

	.class		= &am33xx_l4_hwmod_class,

	.clkdm_name	= "l4ls_clkdm",

	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "l4ls_gclk",

	.prcm		= {

		.omap4	= {
@@ -134,7 +134,7 @@ static struct omap_hwmod am33xx_l4_hs_hwmod = { 
	.name		= "l4_hs",

	.class		= &am33xx_l4_hwmod_class,

	.clkdm_name	= "l4hs_clkdm",

	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "l4hs_gclk",

	.prcm		= {

		.omap4	= {
@@ -150,7 +150,7 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = { 
	.name		= "l4_wkup",

	.class		= &am33xx_l4_hwmod_class,

	.clkdm_name	= "l4_wkup_clkdm",

	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),

	.flags		= HWMOD_INIT_NO_IDLE,

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
@@ -170,7 +170,7 @@ static struct omap_hwmod am33xx_mpu_hwmod = { 
	.name		= "mpu",

	.class		= &am33xx_mpu_hwmod_class,

	.clkdm_name	= "mpu_clkdm",

	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "dpll_mpu_m2_ck",

	.prcm		= {

		.omap4	= {
@@ -450,7 +450,7 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = { 
	.name		= "ocmcram",

	.class		= &am33xx_ocmcram_hwmod_class,

	.clkdm_name	= "l3_clkdm",

	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "l3_gclk",

	.prcm		= {

		.omap4	= {
@@ -532,7 +532,7 @@ static struct omap_hwmod am33xx_control_hwmod = { 
	.name		= "control",

	.class		= &am33xx_control_hwmod_class,

	.clkdm_name	= "l4_wkup_clkdm",

	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "dpll_core_m4_div2_ck",

	.prcm		= {

		.omap4	= {
@@ -1278,8 +1278,21 @@ static struct omap_hwmod am33xx_spi1_hwmod = { 
 * spinlock provides hardware assistance for synchronizing the

 * processes running on multiple processors

 */



static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |

			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {

	.name		= "spinlock",

	.sysc		= &am33xx_spinlock_sysc,

};



static struct omap_hwmod am33xx_spinlock_hwmod = {
@@ -2480,6 +2493,41 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* rng */

static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {

	.rev_offs	= 0x1fe0,

	.sysc_offs	= 0x1fe4,

	.sysc_flags	= SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,

	.idlemodes	= SIDLE_FORCE | SIDLE_NO,

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class am33xx_rng_hwmod_class = {

	.name		= "rng",

	.sysc		= &am33xx_rng_sysc,

};



static struct omap_hwmod am33xx_rng_hwmod = {

	.name		= "rng",

	.class		= &am33xx_rng_hwmod_class,

	.clkdm_name	= "l4ls_clkdm",

	.flags		= HWMOD_SWSUP_SIDLE,

	.main_clk	= "rng_fck",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {

	.master		= &am33xx_l4_ls_hwmod,

	.slave		= &am33xx_rng_hwmod,

	.clk		= "rng_fck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {

	&am33xx_l3_main__emif,

	&am33xx_mpu__l3_main,
@@ -2559,6 +2607,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { 
	&am33xx_cpgmac0__mdio,

	&am33xx_l3_main__sha0,

	&am33xx_l3_main__aes0,

	&am33xx_l4_per__rng,

	NULL,

};

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

+48 −0
Original line number Diff line number Diff line
@@ -3693,6 +3693,53 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/*

 * 'ssi' class

 * synchronous serial interface (multichannel and full-duplex serial if)

 */



static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |

			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |

			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |

			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {

	.name	= "ssi",

	.sysc	= &omap34xx_ssi_sysc,

};



static struct omap_hwmod omap34xx_ssi_hwmod = {

	.name		= "ssi",

	.class		= &omap34xx_ssi_hwmod_class,

	.clkdm_name	= "core_l4_clkdm",

	.main_clk	= "ssi_ssr_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id		= 1,

			.module_bit		= OMAP3430_EN_SSI_SHIFT,

			.module_offs		= CORE_MOD,

			.idlest_reg_id		= 1,

			.idlest_idle_bit	= OMAP3430ES2_ST_SSI_IDLE_SHIFT,

		},

	},

};



/* L4 CORE -> SSI */

static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {

	.master		= &omap3xxx_l4_core_hwmod,

	.slave		= &omap34xx_ssi_hwmod,

	.clk		= "ssi_ick",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {

	&omap3xxx_l3_main__l4_core,

	&omap3xxx_l3_main__l4_per,
@@ -3818,6 +3865,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { 
#ifdef CONFIG_OMAP_IOMMU_IVA2

	&omap3xxx_l3_main__mmu_iva,

#endif

	&omap34xx_l4_core__ssi,

	NULL

};

arch/arm/mach-omap2/omap_hwmod_44xx_data.c

+3 −3
Original line number Diff line number Diff line
@@ -914,7 +914,7 @@ static struct omap_hwmod omap44xx_emif1_hwmod = { 
	.name		= "emif1",

	.class		= &omap44xx_emif_hwmod_class,

	.clkdm_name	= "l3_emif_clkdm",

	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "ddrphy_ck",

	.prcm = {

		.omap4 = {
@@ -930,7 +930,7 @@ static struct omap_hwmod omap44xx_emif2_hwmod = { 
	.name		= "emif2",

	.class		= &omap44xx_emif_hwmod_class,

	.clkdm_name	= "l3_emif_clkdm",

	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "ddrphy_ck",

	.prcm = {

		.omap4 = {
@@ -2193,7 +2193,7 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { 
	.name		= "mpu",

	.class		= &omap44xx_mpu_hwmod_class,

	.clkdm_name	= "mpuss_clkdm",

	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "dpll_mpu_m2_ck",

	.prcm = {

		.omap4 = {

arch/arm/mach-omap2/omap_hwmod_54xx_data.c

+227 −3
Original line number Diff line number Diff line
@@ -352,7 +352,7 @@ static struct omap_hwmod omap54xx_emif1_hwmod = { 
	.name		= "emif1",

	.class		= &omap54xx_emif_hwmod_class,

	.clkdm_name	= "emif_clkdm",

	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "dpll_core_h11x2_ck",

	.prcm = {

		.omap4 = {
@@ -368,7 +368,7 @@ static struct omap_hwmod omap54xx_emif2_hwmod = { 
	.name		= "emif2",

	.class		= &omap54xx_emif_hwmod_class,

	.clkdm_name	= "emif_clkdm",

	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "dpll_core_h11x2_ck",

	.prcm = {

		.omap4 = {
@@ -1135,7 +1135,7 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { 
	.name		= "mpu",

	.class		= &omap54xx_mpu_hwmod_class,

	.clkdm_name	= "mpu_clkdm",

	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "dpll_mpu_m2_ck",

	.prcm = {

		.omap4 = {
@@ -1145,6 +1145,77 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { 
	},

};



/*

 * 'spinlock' class

 * spinlock provides hardware assistance for synchronizing the processes

 * running on multiple processors

 */



static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |

			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {

	.name	= "spinlock",

	.sysc	= &omap54xx_spinlock_sysc,

};



/* spinlock */

static struct omap_hwmod omap54xx_spinlock_hwmod = {

	.name		= "spinlock",

	.class		= &omap54xx_spinlock_hwmod_class,

	.clkdm_name	= "l4cfg_clkdm",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,

			.context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,

		},

	},

};



/*

 * 'ocp2scp' class

 * bridge to transform ocp interface protocol to scp (serial control port)

 * protocol

 */



static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |

			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {

	.name	= "ocp2scp",

	.sysc	= &omap54xx_ocp2scp_sysc,

};



/* ocp2scp1 */

static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {

	.name		= "ocp2scp1",

	.class		= &omap54xx_ocp2scp_hwmod_class,

	.clkdm_name	= "l3init_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,

			.context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_HWCTRL,

		},

	},

};



/*

 * 'timer' class

 * general purpose timer module with accurate 1ms tick
@@ -1464,6 +1535,123 @@ static struct omap_hwmod omap54xx_uart6_hwmod = { 
	},

};



/*

 * 'usb_host_hs' class

 * high-speed multi-port usb host controller

 */



static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |

			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |

			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |

			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),

	.sysc_fields	= &omap_hwmod_sysc_type2,

};



static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {

	.name	= "usb_host_hs",

	.sysc	= &omap54xx_usb_host_hs_sysc,

};



static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {

	.name		= "usb_host_hs",

	.class		= &omap54xx_usb_host_hs_hwmod_class,

	.clkdm_name	= "l3init_clkdm",

	/*

	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock

	 * id: i660

	 *

	 * Description:

	 * In the following configuration :

	 * - USBHOST module is set to smart-idle mode

	 * - PRCM asserts idle_req to the USBHOST module ( This typically

	 *   happens when the system is going to a low power mode : all ports

	 *   have been suspended, the master part of the USBHOST module has

	 *   entered the standby state, and SW has cut the functional clocks)

	 * - an USBHOST interrupt occurs before the module is able to answer

	 *   idle_ack, typically a remote wakeup IRQ.

	 * Then the USB HOST module will enter a deadlock situation where it

	 * is no more accessible nor functional.

	 *

	 * Workaround:

	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE

	 */



	/*

	 * Errata: USB host EHCI may stall when entering smart-standby mode

	 * Id: i571

	 *

	 * Description:

	 * When the USBHOST module is set to smart-standby mode, and when it is

	 * ready to enter the standby state (i.e. all ports are suspended and

	 * all attached devices are in suspend mode), then it can wrongly assert

	 * the Mstandby signal too early while there are still some residual OCP

	 * transactions ongoing. If this condition occurs, the internal state

	 * machine may go to an undefined state and the USB link may be stuck

	 * upon the next resume.

	 *

	 * Workaround:

	 * Don't use smart standby; use only force standby,

	 * hence HWMOD_SWSUP_MSTANDBY

	 */



	/*

	 * During system boot; If the hwmod framework resets the module

	 * the module will have smart idle settings; which can lead to deadlock

	 * (above Errata Id:i660); so, dont reset the module during boot;

	 * Use HWMOD_INIT_NO_RESET.

	 */



	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |

			  HWMOD_INIT_NO_RESET,

	.main_clk	= "l3init_60m_fclk",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,

			.context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

};



/*

 * 'usb_tll_hs' class

 * usb_tll_hs module is the adapter on the usb_host_hs ports

 */



static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |

			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {

	.name	= "usb_tll_hs",

	.sysc	= &omap54xx_usb_tll_hs_sysc,

};



static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {

	.name		= "usb_tll_hs",

	.class		= &omap54xx_usb_tll_hs_hwmod_class,

	.clkdm_name	= "l3init_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,

			.context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_HWCTRL,

		},

	},

};



/*

 * 'usb_otg_ss' class

 * 2.0 super speed (usb_otg_ss) controller
@@ -1960,6 +2148,22 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> spinlock */

static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {

	.master		= &omap54xx_l4_cfg_hwmod,

	.slave		= &omap54xx_spinlock_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> ocp2scp1 */

static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {

	.master		= &omap54xx_l4_cfg_hwmod,

	.slave		= &omap54xx_ocp2scp1_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_wkup -> timer1 */

static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {

	.master		= &omap54xx_l4_wkup_hwmod,
@@ -2096,6 +2300,22 @@ static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> usb_host_hs */

static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {

	.master		= &omap54xx_l4_cfg_hwmod,

	.slave		= &omap54xx_usb_host_hs_hwmod,

	.clk		= "l3_iclk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> usb_tll_hs */

static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {

	.master		= &omap54xx_l4_cfg_hwmod,

	.slave		= &omap54xx_usb_tll_hs_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_cfg -> usb_otg_ss */

static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {

	.master		= &omap54xx_l4_cfg_hwmod,
@@ -2163,6 +2383,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { 
	&omap54xx_l4_per__mmc4,

	&omap54xx_l4_per__mmc5,

	&omap54xx_l4_cfg__mpu,

	&omap54xx_l4_cfg__spinlock,

	&omap54xx_l4_cfg__ocp2scp1,

	&omap54xx_l4_wkup__timer1,

	&omap54xx_l4_per__timer2,

	&omap54xx_l4_per__timer3,
@@ -2180,6 +2402,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { 
	&omap54xx_l4_per__uart4,

	&omap54xx_l4_per__uart5,

	&omap54xx_l4_per__uart6,

	&omap54xx_l4_cfg__usb_host_hs,

	&omap54xx_l4_cfg__usb_tll_hs,

	&omap54xx_l4_cfg__usb_otg_ss,

	&omap54xx_l4_wkup__wd_timer2,

	NULL,