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Commit a2bb28a0 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'omap7xx-fortony-rc3' of git://robotfuzz.com/linwizard-kernel into omap7xx

parents 012abeea f8631e7b

arch/arm/mach-omap1/board-fsample.c

+9 −9
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ static struct resource smc91x_resources[] = { 
		.flags	= IORESOURCE_MEM,

	},

	[1] = {

		.start	= INT_730_MPU_EXT_NIRQ,

		.start	= INT_7XX_MPU_EXT_NIRQ,

		.end	= 0,

		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,

	},
@@ -196,8 +196,8 @@ static struct platform_device smc91x_device = { 


static struct resource kp_resources[] = {

	[0] = {

		.start	= INT_730_MPUIO_KEYPAD,

		.end	= INT_730_MPUIO_KEYPAD,

		.start	= INT_7XX_MPUIO_KEYPAD,

		.end	= INT_7XX_MPUIO_KEYPAD,

		.flags	= IORESOURCE_IRQ,

	},

};
@@ -309,7 +309,7 @@ static void __init omap_fsample_map_io(void) 
	/*

	 * Hold GSM Reset until needed

	 */

	omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);

	omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);



	/*

	 * UARTs -> done automagically by 8250 driver
@@ -320,21 +320,21 @@ static void __init omap_fsample_map_io(void) 
	 */



	/* Flash: CS0 timings setup */

	omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);

	omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);

	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);

	omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);



	/*

	 * Ethernet support through the debug board

	 * CS1 timings setup

	 */

	omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);

	omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);

	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);

	omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);



	/*

	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,

	 * It is used as the Ethernet controller interrupt

	 */

	omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);

	omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);

}



MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")

arch/arm/mach-omap1/board-perseus2.c

+9 −9
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ static struct resource smc91x_resources[] = { 
		.flags	= IORESOURCE_MEM,

	},

	[1] = {

		.start	= INT_730_MPU_EXT_NIRQ,

		.start	= INT_7XX_MPU_EXT_NIRQ,

		.end	= 0,

		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,

	},
@@ -163,8 +163,8 @@ static struct platform_device smc91x_device = { 


static struct resource kp_resources[] = {

	[0] = {

		.start	= INT_730_MPUIO_KEYPAD,

		.end	= INT_730_MPUIO_KEYPAD,

		.start	= INT_7XX_MPUIO_KEYPAD,

		.end	= INT_7XX_MPUIO_KEYPAD,

		.flags	= IORESOURCE_IRQ,

	},

};
@@ -270,7 +270,7 @@ static void __init omap_perseus2_map_io(void) 
	/*

	 * Hold GSM Reset until needed

	 */

	omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);

	omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);



	/*

	 * UARTs -> done automagically by 8250 driver
@@ -281,21 +281,21 @@ static void __init omap_perseus2_map_io(void) 
	 */



	/* Flash: CS0 timings setup */

	omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);

	omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);

	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);

	omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);



	/*

	 * Ethernet support through the debug board

	 * CS1 timings setup

	 */

	omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);

	omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);

	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);

	omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);



	/*

	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,

	 * It is used as the Ethernet controller interrupt

	 */

	omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);

	omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);

}



MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")

arch/arm/mach-omap1/clock.c

+12 −12
Original line number Diff line number Diff line
@@ -69,13 +69,13 @@ struct omap_clk { 
	}



#define CK_310	(1 << 0)

#define CK_730	(1 << 1)

#define CK_7XX	(1 << 1)

#define CK_1510	(1 << 2)

#define CK_16XX	(1 << 3)



static struct omap_clk omap_clks[] = {

	/* non-ULPD clocks */

	CLK(NULL,	"ck_ref",	&ck_ref,	CK_16XX | CK_1510 | CK_310),

	CLK(NULL,	"ck_ref",	&ck_ref,	CK_16XX | CK_1510 | CK_310 | CK_7XX),

	CLK(NULL,	"ck_dpll1",	&ck_dpll1,	CK_16XX | CK_1510 | CK_310),

	/* CK_GEN1 clocks */

	CLK(NULL,	"ck_dpll1out",	&ck_dpll1out.clk, CK_16XX),
@@ -83,7 +83,7 @@ static struct omap_clk omap_clks[] = { 
	CLK(NULL,	"arm_ck",	&arm_ck,	CK_16XX | CK_1510 | CK_310),

	CLK(NULL,	"armper_ck",	&armper_ck.clk,	CK_16XX | CK_1510 | CK_310),

	CLK(NULL,	"arm_gpio_ck",	&arm_gpio_ck,	CK_1510 | CK_310),

	CLK(NULL,	"armxor_ck",	&armxor_ck.clk,	CK_16XX | CK_1510 | CK_310),

	CLK(NULL,	"armxor_ck",	&armxor_ck.clk,	CK_16XX | CK_1510 | CK_310 | CK_7XX),

	CLK(NULL,	"armtim_ck",	&armtim_ck.clk,	CK_16XX | CK_1510 | CK_310),

	CLK("omap_wdt",	"fck",		&armwdt_ck.clk,	CK_16XX | CK_1510 | CK_310),

	CLK("omap_wdt",	"ick",		&armper_ck.clk,	CK_16XX),
@@ -97,7 +97,7 @@ static struct omap_clk omap_clks[] = { 
	CLK(NULL,	"dspxor_ck",	&dspxor_ck,	CK_16XX | CK_1510 | CK_310),

	CLK(NULL,	"dsptim_ck",	&dsptim_ck,	CK_16XX | CK_1510 | CK_310),

	/* CK_GEN3 clocks */

	CLK(NULL,	"tc_ck",	&tc_ck.clk,	CK_16XX | CK_1510 | CK_310 | CK_730),

	CLK(NULL,	"tc_ck",	&tc_ck.clk,	CK_16XX | CK_1510 | CK_310 | CK_7XX),

	CLK(NULL,	"tipb_ck",	&tipb_ck,	CK_1510 | CK_310),

	CLK(NULL,	"l3_ocpi_ck",	&l3_ocpi_ck,	CK_16XX),

	CLK(NULL,	"tc1_ck",	&tc1_ck,	CK_16XX),
@@ -108,7 +108,7 @@ static struct omap_clk omap_clks[] = { 
	CLK(NULL,	"lb_ck",	&lb_ck.clk,	CK_1510 | CK_310),

	CLK(NULL,	"rhea1_ck",	&rhea1_ck,	CK_16XX),

	CLK(NULL,	"rhea2_ck",	&rhea2_ck,	CK_16XX),

	CLK(NULL,	"lcd_ck",	&lcd_ck_16xx,	CK_16XX | CK_730),

	CLK(NULL,	"lcd_ck",	&lcd_ck_16xx,	CK_16XX | CK_7XX),

	CLK(NULL,	"lcd_ck",	&lcd_ck_1510.clk, CK_1510 | CK_310),

	/* ULPD clocks */

	CLK(NULL,	"uart1_ck",	&uart1_1510,	CK_1510 | CK_310),
@@ -398,7 +398,7 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) 
	 * Reprogramming the DPLL is tricky, it must be done from SRAM.

	 * (on 730, bit 13 must always be 1)

	 */

	if (cpu_is_omap730())

	if (cpu_is_omap7xx())

		omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);

	else

		omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
@@ -783,8 +783,8 @@ int __init omap1_clk_init(void) 
		cpu_mask |= CK_16XX;

	if (cpu_is_omap1510())

		cpu_mask |= CK_1510;

	if (cpu_is_omap730())

		cpu_mask |= CK_730;

	if (cpu_is_omap7xx())

		cpu_mask |= CK_7XX;

	if (cpu_is_omap310())

		cpu_mask |= CK_310;
@@ -800,7 +800,7 @@ int __init omap1_clk_init(void) 
			crystal_type = info->system_clock_type;

	}



#if defined(CONFIG_ARCH_OMAP730)

#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)

	ck_ref.rate = 13000000;

#elif defined(CONFIG_ARCH_OMAP16XX)

	if (crystal_type == 2)
@@ -847,7 +847,7 @@ int __init omap1_clk_init(void) 
		printk(KERN_ERR "System frequencies not set. Check your config.\n");

		/* Guess sane values (60MHz) */

		omap_writew(0x2290, DPLL_CTL);

		omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);

		omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);

		ck_dpll1.rate = 60000000;

	}

#endif
@@ -862,7 +862,7 @@ int __init omap1_clk_init(void) 


#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)

	/* Select slicer output as OMAP input clock */

	omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);

	omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);

#endif



	/* Amstrad Delta wants BCLK high when inactive */
@@ -873,7 +873,7 @@ int __init omap1_clk_init(void) 


	/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */

	/* (on 730, bit 13 must not be cleared) */

	if (cpu_is_omap730())

	if (cpu_is_omap7xx())

		omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);

	else

		omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);

arch/arm/mach-omap1/io.c

+11 −34
Original line number Diff line number Diff line
@@ -36,33 +36,17 @@ static struct map_desc omap_io_desc[] __initdata = { 
	}

};



#ifdef CONFIG_ARCH_OMAP730

static struct map_desc omap730_io_desc[] __initdata = {

#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)

static struct map_desc omap7xx_io_desc[] __initdata = {

	{

		.virtual	= OMAP730_DSP_BASE,

		.pfn		= __phys_to_pfn(OMAP730_DSP_START),

		.length		= OMAP730_DSP_SIZE,

		.virtual	= OMAP7XX_DSP_BASE,

		.pfn		= __phys_to_pfn(OMAP7XX_DSP_START),

		.length		= OMAP7XX_DSP_SIZE,

		.type		= MT_DEVICE

	}, {

		.virtual	= OMAP730_DSPREG_BASE,

		.pfn		= __phys_to_pfn(OMAP730_DSPREG_START),

		.length		= OMAP730_DSPREG_SIZE,

		.type		= MT_DEVICE

	}

};

#endif



#ifdef CONFIG_ARCH_OMAP850

static struct map_desc omap850_io_desc[] __initdata = {

	{

		.virtual	= OMAP850_DSP_BASE,

		.pfn		= __phys_to_pfn(OMAP850_DSP_START),

		.length		= OMAP850_DSP_SIZE,

		.type		= MT_DEVICE

	}, {

		.virtual	= OMAP850_DSPREG_BASE,

		.pfn		= __phys_to_pfn(OMAP850_DSPREG_START),

		.length		= OMAP850_DSPREG_SIZE,

		.virtual	= OMAP7XX_DSPREG_BASE,

		.pfn		= __phys_to_pfn(OMAP7XX_DSPREG_START),

		.length		= OMAP7XX_DSPREG_SIZE,

		.type		= MT_DEVICE

	}

};
@@ -120,18 +104,11 @@ void __init omap1_map_common_io(void) 
	 */

	omap_check_revision();



#ifdef CONFIG_ARCH_OMAP730

	if (cpu_is_omap730()) {

		iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));

	}

#endif



#ifdef CONFIG_ARCH_OMAP850

	if (cpu_is_omap850()) {

		iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc));

#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)

	if (cpu_is_omap7xx()) {

		iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));

	}

#endif



#ifdef CONFIG_ARCH_OMAP15XX

	if (cpu_is_omap15xx()) {

		iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));

arch/arm/mach-omap1/irq.c

+8 −24
Original line number Diff line number Diff line
@@ -137,16 +137,8 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) 
	irq_bank_writel(val, bank, offset);

}



#ifdef CONFIG_ARCH_OMAP730

static struct omap_irq_bank omap730_irq_banks[] = {

	{ .base_reg = OMAP_IH1_BASE,		.trigger_map = 0xb3f8e22f },

	{ .base_reg = OMAP_IH2_BASE,		.trigger_map = 0xfdb9c1f2 },

	{ .base_reg = OMAP_IH2_BASE + 0x100,	.trigger_map = 0x800040f3 },

};

#endif



#ifdef CONFIG_ARCH_OMAP850

static struct omap_irq_bank omap850_irq_banks[] = {

#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)

static struct omap_irq_bank omap7xx_irq_banks[] = {

	{ .base_reg = OMAP_IH1_BASE,		.trigger_map = 0xb3f8e22f },

	{ .base_reg = OMAP_IH2_BASE,		.trigger_map = 0xfdb9c1f2 },

	{ .base_reg = OMAP_IH2_BASE + 0x100,	.trigger_map = 0x800040f3 },
@@ -186,16 +178,10 @@ void __init omap_init_irq(void) 
{

	int i, j;



#ifdef CONFIG_ARCH_OMAP730

	if (cpu_is_omap730()) {

		irq_banks = omap730_irq_banks;

		irq_bank_count = ARRAY_SIZE(omap730_irq_banks);

	}

#endif

#ifdef CONFIG_ARCH_OMAP850

	if (cpu_is_omap850()) {

		irq_banks = omap850_irq_banks;

		irq_bank_count = ARRAY_SIZE(omap850_irq_banks);

#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)

	if (cpu_is_omap7xx()) {

		irq_banks = omap7xx_irq_banks;

		irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);

	}

#endif

#ifdef CONFIG_ARCH_OMAP15XX
@@ -247,10 +233,8 @@ void __init omap_init_irq(void) 


	/* Unmask level 2 handler */



	if (cpu_is_omap730())

		omap_unmask_irq(INT_730_IH2_IRQ);

	else if (cpu_is_omap850())

		omap_unmask_irq(INT_850_IH2_IRQ);

	if (cpu_is_omap7xx())

		omap_unmask_irq(INT_7XX_IH2_IRQ);

	else if (cpu_is_omap15xx())

		omap_unmask_irq(INT_1510_IH2_IRQ);

	else if (cpu_is_omap16xx())