Merge branch 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-next (a1b5fb3d) · Commits · e / devices / android_kernel_teracube_emerald

drivers/gpu/drm/radeon/cik.c

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -1096,7 +1096,7 @@ static const u32 spectre_golden_registers[] =
	0x8a14, 0xf000003f, 0x00000007,		0x8a14, 0xf000003f, 0x00000007,
	0x8b24, 0xffffffff, 0x00ffffff,		0x8b24, 0xffffffff, 0x00ffffff,
	0x28350, 0x3f3f3fff, 0x00000082,		0x28350, 0x3f3f3fff, 0x00000082,
	0x28355, 0x0000003f, 0x00000000,		0x28354, 0x0000003f, 0x00000000,
	0x3e78, 0x00000001, 0x00000002,		0x3e78, 0x00000001, 0x00000002,
	0x913c, 0xffff03df, 0x00000004,		0x913c, 0xffff03df, 0x00000004,
	0xc768, 0x00000008, 0x00000008,		0xc768, 0x00000008, 0x00000008,
	@@ -6542,8 +6542,8 @@ void cik_get_csb_buffer(struct radeon_device rdev, volatile u32 buffer)
	buffer[count++] = cpu_to_le32(0x00000000);		buffer[count++] = cpu_to_le32(0x00000000);
	break;		break;
	case CHIP_HAWAII:		case CHIP_HAWAII:
	buffer[count++] = 0x3a00161a;		buffer[count++] = cpu_to_le32(0x3a00161a);
	buffer[count++] = 0x0000002e;		buffer[count++] = cpu_to_le32(0x0000002e);
	break;		break;
	default:		default:
	buffer[count++] = cpu_to_le32(0x00000000);		buffer[count++] = cpu_to_le32(0x00000000);

drivers/gpu/drm/radeon/radeon_device.c

+6 −4

Original line number	Original line	Diff line number	Diff line
	@@ -1551,11 +1551,13 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
	/* reset hpd state */		/* reset hpd state */
	radeon_hpd_init(rdev);		radeon_hpd_init(rdev);
	/* blat the mode back in */		/* blat the mode back in */
			if (fbcon) {
	drm_helper_resume_force_mode(dev);		drm_helper_resume_force_mode(dev);
	/* turn on display hw */		/* turn on display hw */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
	drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
	}		}
			}

	drm_kms_helper_poll_enable(dev);		drm_kms_helper_poll_enable(dev);
	return 0;		return 0;

drivers/gpu/drm/radeon/radeon_display.c

+154 −90

Original line number	Original line	Diff line number	Diff line
	@@ -34,6 +34,8 @@
	#include <drm/drm_crtc_helper.h>		#include <drm/drm_crtc_helper.h>
	#include <drm/drm_edid.h>		#include <drm/drm_edid.h>

			#include <linux/gcd.h>

	static void avivo_crtc_load_lut(struct drm_crtc *crtc)		static void avivo_crtc_load_lut(struct drm_crtc *crtc)
	{		{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);		struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	@@ -792,6 +794,7 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
	if (radeon_connector->edid) {		if (radeon_connector->edid) {
	drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);		drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
	ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);		ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
			drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
	return ret;		return ret;
	}		}
	drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);		drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
	@@ -799,66 +802,57 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
	}		}

	/* avivo */		/* avivo */
	static void avivo_get_fb_div(struct radeon_pll *pll,
	u32 target_clock,
	u32 post_div,
	u32 ref_div,
	u32 *fb_div,
	u32 *frac_fb_div)
	{
	u32 tmp = post_div * ref_div;

	tmp *= target_clock;		/**
	*fb_div = tmp / pll->reference_freq;		* avivo_reduce_ratio - fractional number reduction
	*frac_fb_div = tmp % pll->reference_freq;		*
			* @nom: nominator
	if (*fb_div > pll->max_feedback_div)		* @den: denominator
	*fb_div = pll->max_feedback_div;		* @nom_min: minimum value for nominator
	else if (*fb_div < pll->min_feedback_div)		* @den_min: minimum value for denominator
	*fb_div = pll->min_feedback_div;		*
	}		* Find the greatest common divisor and apply it on both nominator and
			* denominator, but make nominator and denominator are at least as large
	static u32 avivo_get_post_div(struct radeon_pll *pll,		* as their minimum values.
	u32 target_clock)		*/
			static void avivo_reduce_ratio(unsigned nom, unsigned den,
			unsigned nom_min, unsigned den_min)
	{		{
	u32 vco, post_div, tmp;		unsigned tmp;

	if (pll->flags & RADEON_PLL_USE_POST_DIV)		/* reduce the numbers to a simpler ratio */
	return pll->post_div;		tmp = gcd(nom, den);
			*nom /= tmp;
			*den /= tmp;

	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {		/* make sure nominator is large enough */
	if (pll->flags & RADEON_PLL_IS_LCD)		if (*nom < nom_min) {
	vco = pll->lcd_pll_out_min;		tmp = (nom_min + nom - 1) / nom;
	else		nom = tmp;
	vco = pll->pll_out_min;		den = tmp;
	} else {
	if (pll->flags & RADEON_PLL_IS_LCD)
	vco = pll->lcd_pll_out_max;
	else
	vco = pll->pll_out_max;
	}		}

	post_div = vco / target_clock;		/* make sure the denominator is large enough */
	tmp = vco % target_clock;		if (*den < den_min) {
			tmp = (den_min + den - 1) / den;
	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {		nom = tmp;
	if (tmp)		den = tmp;
	post_div++;
	} else {
	if (!tmp)
	post_div--;
	}		}

	if (post_div > pll->max_post_div)
	post_div = pll->max_post_div;
	else if (post_div < pll->min_post_div)
	post_div = pll->min_post_div;

	return post_div;
	}		}

	#define MAX_TOLERANCE 10		/**
			* radeon_compute_pll_avivo - compute PLL paramaters
			*
			* @pll: information about the PLL
			* @dot_clock_p: resulting pixel clock
			* fb_div_p: resulting feedback divider
			* frac_fb_div_p: fractional part of the feedback divider
			* ref_div_p: resulting reference divider
			* post_div_p: resulting reference divider
			*
			* Try to calculate the PLL parameters to generate the given frequency:
			* dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
			*/
	void radeon_compute_pll_avivo(struct radeon_pll *pll,		void radeon_compute_pll_avivo(struct radeon_pll *pll,
	u32 freq,		u32 freq,
	u32 *dot_clock_p,		u32 *dot_clock_p,
	@@ -867,53 +861,123 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
	u32 *ref_div_p,		u32 *ref_div_p,
	u32 *post_div_p)		u32 *post_div_p)
	{		{
	u32 target_clock = freq / 10;		unsigned fb_div_min, fb_div_max, fb_div;
	u32 post_div = avivo_get_post_div(pll, target_clock);		unsigned post_div_min, post_div_max, post_div;
	u32 ref_div = pll->min_ref_div;		unsigned ref_div_min, ref_div_max, ref_div;
	u32 fb_div = 0, frac_fb_div = 0, tmp;		unsigned post_div_best, diff_best;
			unsigned nom, den, tmp;

	if (pll->flags & RADEON_PLL_USE_REF_DIV)		/* determine allowed feedback divider range */
	ref_div = pll->reference_div;		fb_div_min = pll->min_feedback_div;
			fb_div_max = pll->max_feedback_div;

	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {		if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
	avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);		fb_div_min *= 10;
	frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;		fb_div_max *= 10;
	if (frac_fb_div >= 5) {
	frac_fb_div -= 5;
	frac_fb_div = frac_fb_div / 10;
	frac_fb_div++;
	}
	if (frac_fb_div >= 10) {
	fb_div++;
	frac_fb_div = 0;
	}		}

			/* determine allowed ref divider range */
			if (pll->flags & RADEON_PLL_USE_REF_DIV)
			ref_div_min = pll->reference_div;
			else
			ref_div_min = pll->min_ref_div;
			ref_div_max = pll->max_ref_div;

			/* determine allowed post divider range */
			if (pll->flags & RADEON_PLL_USE_POST_DIV) {
			post_div_min = pll->post_div;
			post_div_max = pll->post_div;
	} else {		} else {
	while (ref_div <= pll->max_ref_div) {		unsigned target_clock = freq / 10;
	avivo_get_fb_div(pll, target_clock, post_div, ref_div,		unsigned vco_min, vco_max;
	&fb_div, &frac_fb_div);
	if (frac_fb_div >= (pll->reference_freq / 2))		if (pll->flags & RADEON_PLL_IS_LCD) {
	fb_div++;		vco_min = pll->lcd_pll_out_min;
	frac_fb_div = 0;		vco_max = pll->lcd_pll_out_max;
	tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);		} else {
	tmp = (tmp * 10000) / target_clock;		vco_min = pll->pll_out_min;
			vco_max = pll->pll_out_max;
	if (tmp > (10000 + MAX_TOLERANCE))		}
	ref_div++;
	else if (tmp >= (10000 - MAX_TOLERANCE))		post_div_min = vco_min / target_clock;
	break;		if ((target_clock * post_div_min) < vco_min)
			++post_div_min;
			if (post_div_min < pll->min_post_div)
			post_div_min = pll->min_post_div;

			post_div_max = vco_max / target_clock;
			if ((target_clock * post_div_max) > vco_max)
			--post_div_max;
			if (post_div_max > pll->max_post_div)
			post_div_max = pll->max_post_div;
			}

			/* represent the searched ratio as fractional number */
			nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10;
			den = pll->reference_freq;

			/* reduce the numbers to a simpler ratio */
			avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);

			/* now search for a post divider */
			if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
			post_div_best = post_div_min;
	else		else
	ref_div++;		post_div_best = post_div_max;
			diff_best = ~0;

			for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
			unsigned diff = abs(den - den / post_div * post_div);
			if (diff < diff_best \|\| (diff == diff_best &&
			!(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {

			post_div_best = post_div;
			diff_best = diff;
	}		}
	}		}
			post_div = post_div_best;

	dot_clock_p = ((pll->reference_freq fb_div * 10) + (pll->reference_freq * frac_fb_div)) /		/* get matching reference and feedback divider */
	(ref_div * post_div * 10);		ref_div = max(den / post_div, 1u);
			fb_div = nom;

			/* we're almost done, but reference and feedback
			divider might be to large now */

			tmp = ref_div;

			if (fb_div > fb_div_max) {
			ref_div = ref_div * fb_div_max / fb_div;
			fb_div = fb_div_max;
			}

			if (ref_div > ref_div_max) {
			ref_div = ref_div_max;
			fb_div = nom * ref_div_max / tmp;
			}

			/* reduce the numbers to a simpler ratio once more */
			/* this also makes sure that the reference divider is large enough */
			avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);

			/* and finally save the result */
			if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
			*fb_div_p = fb_div / 10;
			*frac_fb_div_p = fb_div % 10;
			} else {
	*fb_div_p = fb_div;		*fb_div_p = fb_div;
	*frac_fb_div_p = frac_fb_div;		*frac_fb_div_p = 0;
			}

			dot_clock_p = ((pll->reference_freq fb_div_p 10) +
			(pll->reference_freq * *frac_fb_div_p)) /
			(ref_div * post_div * 10);
	*ref_div_p = ref_div;		*ref_div_p = ref_div;
	*post_div_p = post_div;		*post_div_p = post_div;
	DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
	*dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);		DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
			freq, dot_clock_p, fb_div_p, *frac_fb_div_p,
			ref_div, post_div);
	}		}

	/* pre-avivo */		/* pre-avivo */

drivers/gpu/drm/radeon/radeon_drv.c

+12 −5

Original line number	Original line	Diff line number	Diff line
	@@ -405,11 +405,15 @@ static int radeon_pmops_runtime_suspend(struct device *dev)
	struct drm_device *drm_dev = pci_get_drvdata(pdev);		struct drm_device *drm_dev = pci_get_drvdata(pdev);
	int ret;		int ret;

	if (radeon_runtime_pm == 0)		if (radeon_runtime_pm == 0) {
	return -EINVAL;		pm_runtime_forbid(dev);
			return -EBUSY;
			}

	if (radeon_runtime_pm == -1 && !radeon_is_px())		if (radeon_runtime_pm == -1 && !radeon_is_px()) {
	return -EINVAL;		pm_runtime_forbid(dev);
			return -EBUSY;
			}

	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
	drm_kms_helper_poll_disable(drm_dev);		drm_kms_helper_poll_disable(drm_dev);
	@@ -458,12 +462,15 @@ static int radeon_pmops_runtime_idle(struct device *dev)
	struct drm_device *drm_dev = pci_get_drvdata(pdev);		struct drm_device *drm_dev = pci_get_drvdata(pdev);
	struct drm_crtc *crtc;		struct drm_crtc *crtc;

	if (radeon_runtime_pm == 0)		if (radeon_runtime_pm == 0) {
			pm_runtime_forbid(dev);
	return -EBUSY;		return -EBUSY;
			}

	/* are we PX enabled? */		/* are we PX enabled? */
	if (radeon_runtime_pm == -1 && !radeon_is_px()) {		if (radeon_runtime_pm == -1 && !radeon_is_px()) {
	DRM_DEBUG_DRIVER("failing to power off - not px\n");		DRM_DEBUG_DRIVER("failing to power off - not px\n");
			pm_runtime_forbid(dev);
	return -EBUSY;		return -EBUSY;
	}		}

drivers/gpu/drm/radeon/radeon_ring.c

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -262,6 +262,7 @@ int radeon_ib_ring_tests(struct radeon_device *rdev)
	r = radeon_ib_test(rdev, i, ring);		r = radeon_ib_test(rdev, i, ring);
	if (r) {		if (r) {
	ring->ready = false;		ring->ready = false;
			rdev->needs_reset = false;

	if (i == RADEON_RING_TYPE_GFX_INDEX) {		if (i == RADEON_RING_TYPE_GFX_INDEX) {
	/* oh, oh, that's really bad */		/* oh, oh, that's really bad */