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Commit a19a6d11 authored Feb 09, 2010 by Sheng Yang Committed by Marcelo Tosatti Mar 01, 2010

KVM: VMX: Rename VMX_EPT_IGMT_BIT to VMX_EPT_IPAT_BIT



Following the new SDM. Now the bit is named "Ignore PAT memory type".

Signed-off-by: Sheng Yang <sheng@linux.intel.com>
Signed-off-by: Avi Kivity <avi@redhat.com>

parent 90bb6fc5

arch/x86/include/asm/vmx.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -377,7 +377,7 @@ enum vmcs_field {
	#define VMX_EPT_READABLE_MASK 0x1ull		#define VMX_EPT_READABLE_MASK 0x1ull
	#define VMX_EPT_WRITABLE_MASK 0x2ull		#define VMX_EPT_WRITABLE_MASK 0x2ull
	#define VMX_EPT_EXECUTABLE_MASK 0x4ull		#define VMX_EPT_EXECUTABLE_MASK 0x4ull
	#define VMX_EPT_IGMT_BIT (1ull << 6)		#define VMX_EPT_IPAT_BIT (1ull << 6)

	#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul		#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul

arch/x86/kvm/vmx.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -4001,7 +4001,7 @@ static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
	* b. VT-d with snooping control feature: snooping control feature of		* b. VT-d with snooping control feature: snooping control feature of
	* VT-d engine can guarantee the cache correctness. Just set it		* VT-d engine can guarantee the cache correctness. Just set it
	* to WB to keep consistent with host. So the same as item 3.		* to WB to keep consistent with host. So the same as item 3.
	* 3. EPT without VT-d: always map as WB and set IGMT=1 to keep		* 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
	* consistent with host MTRR		* consistent with host MTRR
	*/		*/
	if (is_mmio)		if (is_mmio)
	@@ -4012,7 +4012,7 @@ static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
	VMX_EPT_MT_EPTE_SHIFT;		VMX_EPT_MT_EPTE_SHIFT;
	else		else
	ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)		ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
	\| VMX_EPT_IGMT_BIT;		\| VMX_EPT_IPAT_BIT;

	return ret;		return ret;
	}		}