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Commit a0dc5cb5 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
Browse files

irqchip: mips-gic: Simplify gic_local_irq_domain_map() 



Simplify gic_local_irq_domain_map() by:

- Moving the check for invalid IRQs outside of the loop.

- Moving the decision about whether to use gic_cpu_pin or timer_cpu_pin
  outside of the loop.

- Using the new write_gic_vo_map() accessor function to avoid the need
  to handle each map register separately.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17027/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e98fcb2a

drivers/irqchip/irq-mips-gic.c

+16 −41
Original line number Diff line number Diff line
@@ -498,58 +498,33 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, 
				    irq_hw_number_t hw)

{

	int intr = GIC_HWIRQ_TO_LOCAL(hw);

	int ret = 0;

	int i;

	unsigned long flags;

	u32 val;



	if (!gic_local_irq_is_routable(intr))

		return -EPERM;



	spin_lock_irqsave(&gic_lock, flags);

	for (i = 0; i < gic_vpes; i++) {

		u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;



		gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),

			  mips_cm_vp_id(i));

	if (intr > GIC_LOCAL_INT_FDC) {

		pr_err("Invalid local IRQ %d\n", intr);

		return -EINVAL;

	}



		switch (intr) {

		case GIC_LOCAL_INT_WD:

			gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);

			break;

		case GIC_LOCAL_INT_COMPARE:

			gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP),

				    val);

			break;

		case GIC_LOCAL_INT_TIMER:

	if (intr == GIC_LOCAL_INT_TIMER) {

		/* CONFIG_MIPS_CMP workaround (see __gic_init) */

			val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;

			gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),

				    val);

			break;

		case GIC_LOCAL_INT_PERFCTR:

			gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),

				    val);

			break;

		case GIC_LOCAL_INT_SWINT0:

			gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP),

				    val);

			break;

		case GIC_LOCAL_INT_SWINT1:

			gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP),

				    val);

			break;

		case GIC_LOCAL_INT_FDC:

			gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);

			break;

		default:

			pr_err("Invalid local IRQ %d\n", intr);

			ret = -EINVAL;

			break;

		val = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;

	} else {

		val = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;

	}



	spin_lock_irqsave(&gic_lock, flags);

	for (i = 0; i < gic_vpes; i++) {

		write_gic_vl_other(mips_cm_vp_id(i));

		write_gic_vo_map(intr, val);

	}

	spin_unlock_irqrestore(&gic_lock, flags);



	return ret;

	return 0;

}



static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,

include/linux/irqchip/mips-gic.h

+0 −6
Original line number Diff line number Diff line
@@ -84,13 +84,7 @@ 
#define GIC_VPE_MASK_OFS		0x0008

#define GIC_VPE_RMASK_OFS		0x000c

#define GIC_VPE_SMASK_OFS		0x0010

#define GIC_VPE_WD_MAP_OFS		0x0040

#define GIC_VPE_COMPARE_MAP_OFS		0x0044

#define GIC_VPE_TIMER_MAP_OFS		0x0048

#define GIC_VPE_FDC_MAP_OFS		0x004c

#define GIC_VPE_PERFCTR_MAP_OFS		0x0050

#define GIC_VPE_SWINT0_MAP_OFS		0x0054

#define GIC_VPE_SWINT1_MAP_OFS		0x0058

#define GIC_VPE_OTHER_ADDR_OFS		0x0080

#define GIC_VPE_WD_CONFIG0_OFS		0x0090

#define GIC_VPE_WD_COUNT0_OFS		0x0094