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Commit a0c173bd authored by Jacob Pan's avatar Jacob Pan Committed by H. Peter Anvin
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x86, mrst: add cpu type detection 



Medfield is the follow-up of Moorestown, it is treated under the same
HW sub-architecture. However, we do need to know the CPU type in order
for some of the driver to act accordingly.
We also have different optimal clock configuration for each CPU type.

Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
LKML-Reference: <1274295685-6774-3-git-send-email-jacob.jun.pan@linux.intel.com>
Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 1dedefd1

arch/x86/include/asm/mrst.h

+19 −0
Original line number Original line Diff line number Diff line
@@ -11,8 +11,27 @@ 
#ifndef _ASM_X86_MRST_H

#ifndef _ASM_X86_MRST_H

#define _ASM_X86_MRST_H

#define _ASM_X86_MRST_H

extern int pci_mrst_init(void);

extern int pci_mrst_init(void);

extern int mrst_identify_cpu(void);

int __init sfi_parse_mrtc(struct sfi_table_header *table);

int __init sfi_parse_mrtc(struct sfi_table_header *table);





/*

 * Medfield is the follow-up of Moorestown, it combines two chip solution into

 * one. Other than that it also added always-on and constant tsc and lapic

 * timers. Medfield is the platform name, and the chip name is called Penwell

 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be

 * identified via MSRs.

 */

enum mrst_cpu_type {

	MRST_CPU_CHIP_LINCROFT = 1,

	MRST_CPU_CHIP_PENWELL,

};



enum mrst_timer_options {

	MRST_TIMER_DEFAULT,

	MRST_TIMER_APBT_ONLY,

	MRST_TIMER_LAPIC_APBT,

};



#define SFI_MTMR_MAX_NUM 8

#define SFI_MTMR_MAX_NUM 8

#define SFI_MRTC_MAX	8

#define SFI_MRTC_MAX	8

arch/x86/kernel/mrst.c

+26 −0
Original line number Original line Diff line number Diff line
@@ -27,6 +27,8 @@ 




static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];

static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];

static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];

static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];

static int mrst_cpu_chip;



int sfi_mtimer_num;

int sfi_mtimer_num;





struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];

struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
@@ -216,6 +218,28 @@ static void __init mrst_setup_boot_clock(void) 
		setup_boot_APIC_clock();

		setup_boot_APIC_clock();

};

};





int mrst_identify_cpu(void)

{

	return mrst_cpu_chip;

}

EXPORT_SYMBOL_GPL(mrst_identify_cpu);



void __cpuinit mrst_arch_setup(void)

{

	if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)

		mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;

	else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)

		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;

	else {

		pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",

			boot_cpu_data.x86, boot_cpu_data.x86_model);

		mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;

	}

	pr_debug("Moorestown CPU %s identified\n",

		(mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?

		"Lincroft" : "Penwell");

}



/*

/*

 * Moorestown specific x86_init function overrides and early setup

 * Moorestown specific x86_init function overrides and early setup

 * calls.

 * calls.
@@ -230,6 +254,8 @@ void __init x86_mrst_early_setup(void) 




	x86_init.irqs.pre_vector_init = x86_init_noop;

	x86_init.irqs.pre_vector_init = x86_init_noop;





	x86_init.oem.arch_setup = mrst_arch_setup;



	x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;

	x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;





	x86_platform.calibrate_tsc = mrst_calibrate_tsc;

	x86_platform.calibrate_tsc = mrst_calibrate_tsc;