Loading arch/arm/mach-imx/clock.c +1 −1 Original line number Diff line number Diff line Loading @@ -23,7 +23,7 @@ #include <linux/err.h> #include <linux/io.h> #include <mach/imx-regs.h> #include <mach/hardware.h> /* * Very simple approach: We can't disable clocks, so we do Loading arch/arm/mach-imx/generic.c +3 −3 Original line number Diff line number Diff line Loading @@ -245,11 +245,11 @@ void __init imx_set_mmc_info(struct imxmmc_platform_data *info) imx_mmc_device.dev.platform_data = info; } static struct imxfb_mach_info imx_fb_info; static struct imx_fb_platform_data imx_fb_info; void __init set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info) void __init set_imx_fb_info(struct imx_fb_platform_data *hard_imx_fb_info) { memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imxfb_mach_info)); memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imx_fb_platform_data)); } static struct resource imxfb_resources[] = { Loading arch/arm/mach-imx/include/mach/imx-regs.h +0 −106 Original line number Diff line number Diff line Loading @@ -373,110 +373,4 @@ #define TSTAT_CAPT (1<<1) #define TSTAT_COMP (1<<0) /* * LCD Controller */ #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) #define SIZE_YMAX(y) ( (y) & 0x1ff ) #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) #define VPW_VPW(x) ( (x) & 0x3ff ) #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) #define CPOS_CC1 (1<<31) #define CPOS_CC0 (1<<30) #define CPOS_OP (1<<28) #define CPOS_CXP(x) (((x) & 3ff) << 16) #define CPOS_CYP(y) ((y) & 0x1ff) #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) #define LCWHB_BK_EN (1<<31) #define LCWHB_CW(w) (((w) & 0x1f) << 24) #define LCWHB_CH(h) (((h) & 0x1f) << 16) #define LCWHB_BD(x) ((x) & 0xff) #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) #define PCR_TFT (1<<31) #define PCR_COLOR (1<<30) #define PCR_PBSIZ_1 (0<<28) #define PCR_PBSIZ_2 (1<<28) #define PCR_PBSIZ_4 (2<<28) #define PCR_PBSIZ_8 (3<<28) #define PCR_BPIX_1 (0<<25) #define PCR_BPIX_2 (1<<25) #define PCR_BPIX_4 (2<<25) #define PCR_BPIX_8 (3<<25) #define PCR_BPIX_12 (4<<25) #define PCR_BPIX_16 (4<<25) #define PCR_PIXPOL (1<<24) #define PCR_FLMPOL (1<<23) #define PCR_LPPOL (1<<22) #define PCR_CLKPOL (1<<21) #define PCR_OEPOL (1<<20) #define PCR_SCLKIDLE (1<<19) #define PCR_END_SEL (1<<18) #define PCR_END_BYTE_SWAP (1<<17) #define PCR_REV_VS (1<<16) #define PCR_ACD_SEL (1<<15) #define PCR_ACD(x) (((x) & 0x7f) << 8) #define PCR_SCLK_SEL (1<<7) #define PCR_SHARP (1<<6) #define PCR_PCD(x) ((x) & 0x3f) #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) #define HCR_H_WAIT_2(x) ((x) & 0xff) #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) #define VCR_V_WAIT_2(x) ((x) & 0xff) #define LCDC_POS __REG(IMX_LCDC_BASE+0x24) #define POS_POS(x) ((x) & 1f) #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) #define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) #define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) #define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) #define LSCR1_GRAY2(x) (((x) & 0xf) << 4) #define LSCR1_GRAY1(x) (((x) & 0xf)) #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) #define PWMR_CLS(x) (((x) & 0x1ff) << 16) #define PWMR_LDMSK (1<<15) #define PWMR_SCR1 (1<<10) #define PWMR_SCR0 (1<<9) #define PWMR_CC_EN (1<<8) #define PWMR_PW(x) ((x) & 0xff) #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) #define DMACR_BURST (1<<31) #define DMACR_HM(x) (((x) & 0xf) << 16) #define DMACR_TM(x) ((x) &0xf) #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) #define RMCR_LCDC_EN (1<<1) #define RMCR_SELF_REF (1<<0) #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) #define LCDICR_INT_SYN (1<<2) #define LCDICR_INT_CON (1) #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) #define LCDISR_UDR_ERR (1<<3) #define LCDISR_ERR_RES (1<<2) #define LCDISR_EOF (1<<1) #define LCDISR_BOF (1<<0) #endif // _IMX_REGS_H Loading
arch/arm/mach-imx/clock.c +1 −1 Original line number Diff line number Diff line Loading @@ -23,7 +23,7 @@ #include <linux/err.h> #include <linux/io.h> #include <mach/imx-regs.h> #include <mach/hardware.h> /* * Very simple approach: We can't disable clocks, so we do Loading
arch/arm/mach-imx/generic.c +3 −3 Original line number Diff line number Diff line Loading @@ -245,11 +245,11 @@ void __init imx_set_mmc_info(struct imxmmc_platform_data *info) imx_mmc_device.dev.platform_data = info; } static struct imxfb_mach_info imx_fb_info; static struct imx_fb_platform_data imx_fb_info; void __init set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info) void __init set_imx_fb_info(struct imx_fb_platform_data *hard_imx_fb_info) { memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imxfb_mach_info)); memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imx_fb_platform_data)); } static struct resource imxfb_resources[] = { Loading
arch/arm/mach-imx/include/mach/imx-regs.h +0 −106 Original line number Diff line number Diff line Loading @@ -373,110 +373,4 @@ #define TSTAT_CAPT (1<<1) #define TSTAT_COMP (1<<0) /* * LCD Controller */ #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) #define SIZE_YMAX(y) ( (y) & 0x1ff ) #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) #define VPW_VPW(x) ( (x) & 0x3ff ) #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) #define CPOS_CC1 (1<<31) #define CPOS_CC0 (1<<30) #define CPOS_OP (1<<28) #define CPOS_CXP(x) (((x) & 3ff) << 16) #define CPOS_CYP(y) ((y) & 0x1ff) #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) #define LCWHB_BK_EN (1<<31) #define LCWHB_CW(w) (((w) & 0x1f) << 24) #define LCWHB_CH(h) (((h) & 0x1f) << 16) #define LCWHB_BD(x) ((x) & 0xff) #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) #define PCR_TFT (1<<31) #define PCR_COLOR (1<<30) #define PCR_PBSIZ_1 (0<<28) #define PCR_PBSIZ_2 (1<<28) #define PCR_PBSIZ_4 (2<<28) #define PCR_PBSIZ_8 (3<<28) #define PCR_BPIX_1 (0<<25) #define PCR_BPIX_2 (1<<25) #define PCR_BPIX_4 (2<<25) #define PCR_BPIX_8 (3<<25) #define PCR_BPIX_12 (4<<25) #define PCR_BPIX_16 (4<<25) #define PCR_PIXPOL (1<<24) #define PCR_FLMPOL (1<<23) #define PCR_LPPOL (1<<22) #define PCR_CLKPOL (1<<21) #define PCR_OEPOL (1<<20) #define PCR_SCLKIDLE (1<<19) #define PCR_END_SEL (1<<18) #define PCR_END_BYTE_SWAP (1<<17) #define PCR_REV_VS (1<<16) #define PCR_ACD_SEL (1<<15) #define PCR_ACD(x) (((x) & 0x7f) << 8) #define PCR_SCLK_SEL (1<<7) #define PCR_SHARP (1<<6) #define PCR_PCD(x) ((x) & 0x3f) #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) #define HCR_H_WAIT_2(x) ((x) & 0xff) #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) #define VCR_V_WAIT_2(x) ((x) & 0xff) #define LCDC_POS __REG(IMX_LCDC_BASE+0x24) #define POS_POS(x) ((x) & 1f) #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) #define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) #define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) #define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) #define LSCR1_GRAY2(x) (((x) & 0xf) << 4) #define LSCR1_GRAY1(x) (((x) & 0xf)) #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) #define PWMR_CLS(x) (((x) & 0x1ff) << 16) #define PWMR_LDMSK (1<<15) #define PWMR_SCR1 (1<<10) #define PWMR_SCR0 (1<<9) #define PWMR_CC_EN (1<<8) #define PWMR_PW(x) ((x) & 0xff) #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) #define DMACR_BURST (1<<31) #define DMACR_HM(x) (((x) & 0xf) << 16) #define DMACR_TM(x) ((x) &0xf) #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) #define RMCR_LCDC_EN (1<<1) #define RMCR_SELF_REF (1<<0) #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) #define LCDICR_INT_SYN (1<<2) #define LCDICR_INT_CON (1) #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) #define LCDISR_UDR_ERR (1<<3) #define LCDISR_ERR_RES (1<<2) #define LCDISR_EOF (1<<1) #define LCDISR_BOF (1<<0) #endif // _IMX_REGS_H
