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Commit 9e1909b9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86/pti updates from Thomas Gleixner:
 "Another set of melted spectrum updates:

   - Iron out the last late microcode loading issues by actually
     checking whether new microcode is present and preventing the CPU
     synchronization to run into a timeout induced hang.

   - Remove Skylake C2 from the microcode blacklist according to the
     latest Intel documentation

   - Fix the VM86 POPF emulation which traps if VIP is set, but VIF is
     not. Enhance the selftests to catch that kind of issue

   - Annotate indirect calls/jumps for objtool on 32bit. This is not a
     functional issue, but for consistency sake its the right thing to
     do.

   - Fix a jump label build warning observed on SPARC64 which uses 32bit
     storage for the code location which is casted to 64 bit pointer w/o
     extending it to 64bit first.

   - Add two new cpufeature bits. Not really an urgent issue, but
     provides them for both x86 and x86/kvm work. No impact on the
     current kernel"

* 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/microcode: Fix CPU synchronization routine
  x86/microcode: Attempt late loading only when new microcode is present
  x86/speculation: Remove Skylake C2 from Speculation Control microcode blacklist
  jump_label: Fix sparc64 warning
  x86/speculation, objtool: Annotate indirect calls/jumps for objtool on 32-bit kernels
  x86/vm86/32: Fix POPF emulation
  selftests/x86/entry_from_vm86: Add test cases for POPF
  selftests/x86/entry_from_vm86: Exit with 1 if we fail
  x86/cpufeatures: Add Intel PCONFIG cpufeature
  x86/cpufeatures: Add Intel Total Memory Encryption cpufeature
parents df4fe178 bb8c13d6

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Diff line number Diff line
@@ -316,6 +316,7 @@ 
#define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */

#define X86_FEATURE_AVX512_VNNI		(16*32+11) /* Vector Neural Network Instructions */

#define X86_FEATURE_AVX512_BITALG	(16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */

#define X86_FEATURE_TME			(16*32+13) /* Intel Total Memory Encryption */

#define X86_FEATURE_AVX512_VPOPCNTDQ	(16*32+14) /* POPCNT for vectors of DW/QW */

#define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */

#define X86_FEATURE_RDPID		(16*32+22) /* RDPID instruction */
@@ -328,6 +329,7 @@ 
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */

#define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */

arch/x86/include/asm/microcode.h

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ struct device; 


enum ucode_state {

	UCODE_OK	= 0,

	UCODE_NEW,

	UCODE_UPDATED,

	UCODE_NFOUND,

	UCODE_ERROR,

arch/x86/include/asm/nospec-branch.h

+4 −1
Original line number Diff line number Diff line
@@ -183,7 +183,10 @@ 
 * otherwise we'll run out of registers. We don't care about CET

 * here, anyway.

 */

# define CALL_NOSPEC ALTERNATIVE("call *%[thunk_target]\n",	\

# define CALL_NOSPEC						\

	ALTERNATIVE(						\

	ANNOTATE_RETPOLINE_SAFE					\

	"call *%[thunk_target]\n",				\

	"       jmp    904f;\n"					\

	"       .align 16\n"					\

	"901:	call   903f;\n"					\

arch/x86/kernel/cpu/intel.c

+1 −2
Original line number Diff line number Diff line
@@ -105,7 +105,7 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 
/*

 * Early microcode releases for the Spectre v2 mitigation were broken.

 * Information taken from;

 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/microcode-update-guidance.pdf

 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf

 * - https://kb.vmware.com/s/article/52345

 * - Microcode revisions observed in the wild

 * - Release note from 20180108 microcode release
@@ -123,7 +123,6 @@ static const struct sku_microcode spectre_bad_microcodes[] = { 
	{ INTEL_FAM6_KABYLAKE_MOBILE,	0x09,	0x80 },

	{ INTEL_FAM6_SKYLAKE_X,		0x03,	0x0100013e },

	{ INTEL_FAM6_SKYLAKE_X,		0x04,	0x0200003c },

	{ INTEL_FAM6_SKYLAKE_DESKTOP,	0x03,	0xc2 },

	{ INTEL_FAM6_BROADWELL_CORE,	0x04,	0x28 },

	{ INTEL_FAM6_BROADWELL_GT3E,	0x01,	0x1b },

	{ INTEL_FAM6_BROADWELL_XEON_D,	0x02,	0x14 },

arch/x86/kernel/cpu/microcode/amd.c

+21 −13
Original line number Diff line number Diff line
@@ -339,7 +339,7 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) 
		return -EINVAL;



	ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size);

	if (ret != UCODE_OK)

	if (ret > UCODE_UPDATED)

		return -EINVAL;



	return 0;
@@ -683,27 +683,35 @@ static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, 
static enum ucode_state

load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)

{

	struct ucode_patch *p;

	enum ucode_state ret;



	/* free old equiv table */

	free_equiv_cpu_table();



	ret = __load_microcode_amd(family, data, size);



	if (ret != UCODE_OK)

	if (ret != UCODE_OK) {

		cleanup();

		return ret;

	}



	p = find_patch(0);

	if (!p) {

		return ret;

	} else {

		if (boot_cpu_data.microcode == p->patch_id)

			return ret;



		ret = UCODE_NEW;

	}



#ifdef CONFIG_X86_32

	/* save BSP's matching patch for early load */

	if (save) {

		struct ucode_patch *p = find_patch(0);

		if (p) {

	if (!save)

		return ret;



	memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);

			memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),

							       PATCH_MAX_SIZE));

		}

	}

#endif

	memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE));



	return ret;

}