Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9cbb035c authored by Bin Meng's avatar Bin Meng Committed by Cyrille Pitchen
Browse files

spi-nor: intel-spi: Fix number of protected range registers for BYT/LPT 



The number of protected range registers is not the same on BYT/LPT/
BXT. GPR0 only exists on Apollo Lake and its offset is reserved on
other platforms.

Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
parent 824af37e

drivers/mtd/spi-nor/intel-spi.c

+11 −5
Original line number Diff line number Diff line
@@ -67,8 +67,6 @@ 
#define PR_LIMIT_MASK			(0x3fff << PR_LIMIT_SHIFT)

#define PR_RPE				BIT(15)

#define PR_BASE_MASK			0x3fff

/* Last PR is GPR0 */

#define PR_NUM				(5 + 1)



/* Offsets are from @ispi->sregs */

#define SSFSTS_CTL			0x00
@@ -96,14 +94,17 @@ 
#define BYT_BCR				0xfc

#define BYT_BCR_WPD			BIT(0)

#define BYT_FREG_NUM			5

#define BYT_PR_NUM			5



#define LPT_PR				0x74

#define LPT_SSFSTS_CTL			0x90

#define LPT_FREG_NUM			5

#define LPT_PR_NUM			5



#define BXT_PR				0x84

#define BXT_SSFSTS_CTL			0xa0

#define BXT_FREG_NUM			12

#define BXT_PR_NUM			6



#define INTEL_SPI_TIMEOUT		5000 /* ms */

#define INTEL_SPI_FIFO_SZ		64
@@ -117,6 +118,7 @@ 
 * @pregs: Start of protection registers

 * @sregs: Start of software sequencer registers

 * @nregions: Maximum number of regions

 * @pr_num: Maximum number of protected range registers

 * @writeable: Is the chip writeable

 * @swseq: Use SW sequencer in register reads/writes

 * @erase_64k: 64k erase supported
@@ -132,6 +134,7 @@ struct intel_spi { 
	void __iomem *pregs;

	void __iomem *sregs;

	size_t nregions;

	size_t pr_num;

	bool writeable;

	bool swseq;

	bool erase_64k;
@@ -167,7 +170,7 @@ static void intel_spi_dump_regs(struct intel_spi *ispi) 
	for (i = 0; i < ispi->nregions; i++)

		dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,

			readl(ispi->base + FREG(i)));

	for (i = 0; i < PR_NUM; i++)

	for (i = 0; i < ispi->pr_num; i++)

		dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,

			readl(ispi->pregs + PR(i)));
@@ -182,7 +185,7 @@ static void intel_spi_dump_regs(struct intel_spi *ispi) 
		dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));



	dev_dbg(ispi->dev, "Protected regions:\n");

	for (i = 0; i < PR_NUM; i++) {

	for (i = 0; i < ispi->pr_num; i++) {

		u32 base, limit;



		value = readl(ispi->pregs + PR(i));
@@ -286,6 +289,7 @@ static int intel_spi_init(struct intel_spi *ispi) 
		ispi->sregs = ispi->base + BYT_SSFSTS_CTL;

		ispi->pregs = ispi->base + BYT_PR;

		ispi->nregions = BYT_FREG_NUM;

		ispi->pr_num = BYT_PR_NUM;



		if (writeable) {

			/* Disable write protection */
@@ -305,12 +309,14 @@ static int intel_spi_init(struct intel_spi *ispi) 
		ispi->sregs = ispi->base + LPT_SSFSTS_CTL;

		ispi->pregs = ispi->base + LPT_PR;

		ispi->nregions = LPT_FREG_NUM;

		ispi->pr_num = LPT_PR_NUM;

		break;



	case INTEL_SPI_BXT:

		ispi->sregs = ispi->base + BXT_SSFSTS_CTL;

		ispi->pregs = ispi->base + BXT_PR;

		ispi->nregions = BXT_FREG_NUM;

		ispi->pr_num = BXT_PR_NUM;

		ispi->erase_64k = true;

		break;
@@ -652,7 +658,7 @@ static bool intel_spi_is_protected(const struct intel_spi *ispi, 
{

	int i;



	for (i = 0; i < PR_NUM; i++) {

	for (i = 0; i < ispi->pr_num; i++) {

		u32 pr_base, pr_limit, pr_value;



		pr_value = readl(ispi->pregs + PR(i));