Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9c6a73c7 authored by Tom Lendacky's avatar Tom Lendacky Committed by Thomas Gleixner
Browse files

x86/cpu/AMD: Use LFENCE_RDTSC in preference to MFENCE_RDTSC 



With LFENCE now a serializing instruction, use LFENCE_RDTSC in preference
to MFENCE_RDTSC.  However, since the kernel could be running under a
hypervisor that does not support writing that MSR, read the MSR back and
verify that the bit has been set successfully.  If the MSR can be read
and the bit is set, then set the LFENCE_RDTSC feature, otherwise set the
MFENCE_RDTSC feature.

Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarReviewed-by: Borislav Petkov <bp@suse.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Tim Chen <tim.c.chen@linux.intel.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Cc: Paul Turner <pjt@google.com>
Link: https://lkml.kernel.org/r/20180108220932.12580.52458.stgit@tlendack-t1.amdoffice.net
parent e4d0e84e

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -354,6 +354,7 @@ 
#define MSR_FAM10H_NODE_ID		0xc001100c

#define MSR_F10H_DECFG			0xc0011029

#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT	1

#define MSR_F10H_DECFG_LFENCE_SERIALIZE		BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)



/* K8 MSRs */

#define MSR_K8_TOP_MEM1			0xc001001a

arch/x86/kernel/cpu/amd.c

+16 −2
Original line number Diff line number Diff line
@@ -829,6 +829,9 @@ static void init_amd(struct cpuinfo_x86 *c) 
		set_cpu_cap(c, X86_FEATURE_K8);



	if (cpu_has(c, X86_FEATURE_XMM2)) {

		unsigned long long val;

		int ret;



		/*

		 * A serializing LFENCE has less overhead than MFENCE, so

		 * use it for execution serialization.  On families which
@@ -839,9 +842,20 @@ static void init_amd(struct cpuinfo_x86 *c) 
		msr_set_bit(MSR_F10H_DECFG,

			    MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);



		/*

		 * Verify that the MSR write was successful (could be running

		 * under a hypervisor) and only then assume that LFENCE is

		 * serializing.

		 */

		ret = rdmsrl_safe(MSR_F10H_DECFG, &val);

		if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {

			/* A serializing LFENCE stops RDTSC speculation */

			set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);

		} else {

			/* MFENCE stops RDTSC speculation */

			set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);

		}

	}



	/*

	 * Family 0x12 and above processors have APIC timer