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Commit 9c606cd4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux into drm-next 

First feature request for 4.16.  Highlights:
- RV and Vega header cleanups
- TTM operation context support
- 48 bit GPUVM fixes for Vega/RV
- More smatch fixes
- ECC support for vega10
- Resizeable BAR support
- Multi-display sync support in DC
- SR-IOV fixes
- Various scheduler improvements
- GPU reset fixes and vram lost tracking
- Clean up DC/powerplay interfaces
- DCN display fixes
- Various DC fixes

* 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux: (291 commits)
  drm/radeon: Use drm_fb_helper_lastclose() and _poll_changed()
  drm/amdgpu: Use drm_fb_helper_lastclose() and _poll_changed()
  drm/amd/display: Use drm_fb_helper_poll_changed()
  drm/ttm: swap consecutive allocated pooled pages v4
  drm/amdgpu: fix amdgpu_sync_resv v2
  drm/ttm: swap consecutive allocated cached pages v3
  drm/amd/amdgpu: set gtt size according to system memory size only
  drm/amdgpu: Get rid of dep_sync as a seperate object.
  drm/amdgpu: allow specifying vm_block_size for multi level PDs v2
  drm/amdgpu: move validation of the VM size into the VM code
  drm/amdgpu: allow non pot VM size values
  drm/amdgpu: choose number of VM levels based on VM size
  drm/amdgpu: unify VM size handling of Vega10 with older generation
  drm/amdgpu: fix amdgpu_vm_num_entries
  drm/amdgpu: fix VM PD addr shift
  drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)
  drm/amd/display: Don't call dm_log_to_buffer directly in dc_conn_log
  drm/amd/display: Add dm_logger_append_va API
  drm/ttm: Use a static string instead of an array of char *
  drm/amd/display: remove usage of legacy_cursor_update
  ...
parents c5dd52f6 3997eea5

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+21 −8
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ 
#include <drm/amdgpu_drm.h>



#include <kgd_kfd_interface.h>

#include "dm_pp_interface.h"

#include "kgd_pp_interface.h"



#include "amd_shared.h"

#include "amdgpu_mode.h"
@@ -59,7 +61,6 @@ 
#include "amdgpu_sync.h"

#include "amdgpu_ring.h"

#include "amdgpu_vm.h"

#include "amd_powerplay.h"

#include "amdgpu_dpm.h"

#include "amdgpu_acp.h"

#include "amdgpu_uvd.h"
@@ -67,11 +68,11 @@ 
#include "amdgpu_vcn.h"

#include "amdgpu_mn.h"

#include "amdgpu_dm.h"



#include "gpu_scheduler.h"

#include "amdgpu_virt.h"

#include "amdgpu_gart.h"





/*

 * Modules parameters.

 */
@@ -177,6 +178,10 @@ extern int amdgpu_cik_support; 
#define CIK_CURSOR_WIDTH 128

#define CIK_CURSOR_HEIGHT 128



/* GPU RESET flags */

#define AMDGPU_RESET_INFO_VRAM_LOST  (1 << 0)

#define AMDGPU_RESET_INFO_FULLRESET  (1 << 1)



struct amdgpu_device;

struct amdgpu_ib;

struct amdgpu_cs_parser;
@@ -735,6 +740,7 @@ struct amdgpu_ctx { 
	struct amdgpu_device    *adev;

	struct amdgpu_queue_mgr queue_mgr;

	unsigned		reset_counter;

	unsigned        reset_counter_query;

	uint32_t		vram_lost_counter;

	spinlock_t		ring_lock;

	struct dma_fence	**fences;
@@ -743,6 +749,7 @@ struct amdgpu_ctx { 
	enum amd_sched_priority init_priority;

	enum amd_sched_priority override_priority;

	struct mutex            lock;

	atomic_t	guilty;

};



struct amdgpu_ctx_mgr {
@@ -1114,7 +1121,6 @@ struct amdgpu_job { 
	struct amdgpu_vm	*vm;

	struct amdgpu_ring	*ring;

	struct amdgpu_sync	sync;

	struct amdgpu_sync	dep_sync;

	struct amdgpu_sync	sched_sync;

	struct amdgpu_ib	*ibs;

	struct dma_fence	*fence; /* the hw fence */
@@ -1405,6 +1411,7 @@ struct amdgpu_fw_vram_usage { 
};



int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);

void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev);



/*

 * CGS
@@ -1421,6 +1428,13 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 
typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);



struct amd_powerplay {

	struct cgs_device *cgs_device;

	void *pp_handle;

	const struct amd_ip_funcs *ip_funcs;

	const struct amd_pm_funcs *pp_funcs;

};



#define AMDGPU_RESET_MAGIC_NUM 64

struct amdgpu_device {

	struct device			*dev;
@@ -1616,9 +1630,6 @@ struct amdgpu_device { 
	/* link all shadow bo */

	struct list_head                shadow_list;

	struct mutex                    shadow_list_lock;

	/* link all gtt */

	spinlock_t			gtt_list_lock;

	struct list_head                gtt_list;

	/* keep an lru list of rings by HW IP */

	struct list_head		ring_lru_list;

	spinlock_t			ring_lru_list_lock;
@@ -1629,7 +1640,8 @@ struct amdgpu_device { 


	/* record last mm index being written through WREG32*/

	unsigned long last_mm_index;

	bool                            in_sriov_reset;

	bool                            in_gpu_reset;

	struct mutex  lock_reset;

};



static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1823,7 +1835,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))



/* Common functions */

int amdgpu_gpu_reset(struct amdgpu_device *adev);

int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job);

bool amdgpu_need_backup(struct amdgpu_device *adev);

void amdgpu_pci_config_reset(struct amdgpu_device *adev);

bool amdgpu_need_post(struct amdgpu_device *adev);
@@ -1835,6 +1847,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 
bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);

void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);

void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);

int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);

void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);

int amdgpu_ttm_init(struct amdgpu_device *adev);

void amdgpu_ttm_fini(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 
		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();

		break;

	default:

		dev_info(adev->dev, "kfd not supported on this ASIC\n");

		dev_dbg(adev->dev, "kfd not supported on this ASIC\n");

		return;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

+4 −4
Original line number Diff line number Diff line
@@ -690,11 +690,11 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) 
			le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);

		/* set a reasonable default for DP */

		if (adev->clock.default_dispclk < 53900) {

			DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",

			DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n",

				  adev->clock.default_dispclk / 100);

			adev->clock.default_dispclk = 60000;

		} else if (adev->clock.default_dispclk <= 60000) {

			DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n",

			DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n",

				  adev->clock.default_dispclk / 100);

			adev->clock.default_dispclk = 62500;

		}

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+0 −2
Original line number Diff line number Diff line
@@ -948,7 +948,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, 
								(amdgpu_crtc->v_border * 2);

					mode_info->vblank_time_us = vblank_lines * line_time_us;

					mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);

					mode_info->ref_clock = adev->clock.spll.reference_freq;

					mode_info = NULL;

				}

			}
@@ -958,7 +957,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, 
		if (mode_info != NULL) {

			mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;

			mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;

			mode_info->ref_clock = adev->clock.spll.reference_freq;

		}

	}

	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+33 −29
Original line number Diff line number Diff line
@@ -90,6 +90,12 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 
		goto free_chunk;

	}



	/* skip guilty context job */

	if (atomic_read(&p->ctx->guilty) == 1) {

		ret = -ECANCELED;

		goto free_chunk;

	}



	mutex_lock(&p->ctx->lock);



	/* get chunks */
@@ -337,7 +343,7 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, 
				 struct amdgpu_bo *bo)

{

	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);

	u64 initial_bytes_moved, bytes_moved;

	struct ttm_operation_ctx ctx = { true, false };

	uint32_t domain;

	int r;
@@ -367,15 +373,13 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, 


retry:

	amdgpu_ttm_placement_from_domain(bo, domain);

	initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);

	r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);

	bytes_moved = atomic64_read(&adev->num_bytes_moved) -

		      initial_bytes_moved;

	p->bytes_moved += bytes_moved;

	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);



	p->bytes_moved += ctx.bytes_moved;

	if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&

	    bo->tbo.mem.mem_type == TTM_PL_VRAM &&

	    bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)

		p->bytes_moved_vis += bytes_moved;

		p->bytes_moved_vis += ctx.bytes_moved;



	if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {

		domain = bo->allowed_domains;
@@ -390,6 +394,7 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, 
				struct amdgpu_bo *validated)

{

	uint32_t domain = validated->allowed_domains;

	struct ttm_operation_ctx ctx = { true, false };

	int r;



	if (!p->evictable)
@@ -431,7 +436,7 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, 
			bo->tbo.mem.mem_type == TTM_PL_VRAM &&

			bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT;

		initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);

		r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);

		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);

		bytes_moved = atomic64_read(&adev->num_bytes_moved) -

			initial_bytes_moved;

		p->bytes_moved += bytes_moved;
@@ -470,6 +475,7 @@ static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo) 
static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,

			    struct list_head *validated)

{

	struct ttm_operation_ctx ctx = { true, false };

	struct amdgpu_bo_list_entry *lobj;

	int r;
@@ -487,8 +493,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, 
		    lobj->user_pages) {

			amdgpu_ttm_placement_from_domain(bo,

							 AMDGPU_GEM_DOMAIN_CPU);

			r = ttm_bo_validate(&bo->tbo, &bo->placement, true,

					    false);

			r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);

			if (r)

				return r;

			amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
@@ -678,7 +683,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 
	if (!r && p->uf_entry.robj) {

		struct amdgpu_bo *uf = p->uf_entry.robj;



		r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);

		r = amdgpu_ttm_alloc_gart(&uf->tbo);

		p->job->uf_addr += amdgpu_bo_gpu_offset(uf);

	}
@@ -781,7 +786,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) 
		return r;



	r = amdgpu_sync_fence(adev, &p->job->sync,

			      fpriv->prt_va->last_pt_update);

			      fpriv->prt_va->last_pt_update, false);

	if (r)

		return r;
@@ -795,7 +800,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) 
			return r;



		f = bo_va->last_pt_update;

		r = amdgpu_sync_fence(adev, &p->job->sync, f);

		r = amdgpu_sync_fence(adev, &p->job->sync, f, false);

		if (r)

			return r;

	}
@@ -818,7 +823,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) 
				return r;



			f = bo_va->last_pt_update;

			r = amdgpu_sync_fence(adev, &p->job->sync, f);

			r = amdgpu_sync_fence(adev, &p->job->sync, f, false);

			if (r)

				return r;

		}
@@ -829,7 +834,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) 
	if (r)

		return r;



	r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update);

	r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);

	if (r)

		return r;
@@ -865,8 +870,8 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, 
			struct amdgpu_bo_va_mapping *m;

			struct amdgpu_bo *aobj = NULL;

			struct amdgpu_cs_chunk *chunk;

			uint64_t offset, va_start;

			struct amdgpu_ib *ib;

			uint64_t offset;

			uint8_t *kptr;



			chunk = &p->chunks[i];
@@ -876,14 +881,14 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, 
			if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)

				continue;



			r = amdgpu_cs_find_mapping(p, chunk_ib->va_start,

						   &aobj, &m);

			va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;

			r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);

			if (r) {

				DRM_ERROR("IB va_start is invalid\n");

				return r;

			}



			if ((chunk_ib->va_start + chunk_ib->ib_bytes) >

			if ((va_start + chunk_ib->ib_bytes) >

			    (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {

				DRM_ERROR("IB va_start+ib_bytes is invalid\n");

				return -EINVAL;
@@ -896,7 +901,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, 
			}



			offset = m->start * AMDGPU_GPU_PAGE_SIZE;

			kptr += chunk_ib->va_start - offset;

			kptr += va_start - offset;



			memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);

			amdgpu_bo_kunmap(aobj);
@@ -1033,8 +1038,8 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, 
			amdgpu_ctx_put(ctx);

			return r;

		} else if (fence) {

			r = amdgpu_sync_fence(p->adev, &p->job->sync,

					      fence);

			r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,

					true);

			dma_fence_put(fence);

			amdgpu_ctx_put(ctx);

			if (r)
@@ -1053,7 +1058,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, 
	if (r)

		return r;



	r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);

	r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);

	dma_fence_put(fence);



	return r;
@@ -1194,11 +1199,10 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
	job->uf_sequence = seq;



	amdgpu_job_free_resources(job);

	amdgpu_ring_priority_get(job->ring,

				 amd_sched_get_job_priority(&job->base));

	amdgpu_ring_priority_get(job->ring, job->base.s_priority);



	trace_amdgpu_cs_ioctl(job);

	amd_sched_entity_push_job(&job->base);

	amd_sched_entity_push_job(&job->base, entity);



	ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);

	amdgpu_mn_unlock(p->mn);
@@ -1570,6 +1574,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 
			   struct amdgpu_bo_va_mapping **map)

{

	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;

	struct ttm_operation_ctx ctx = { false, false };

	struct amdgpu_vm *vm = &fpriv->vm;

	struct amdgpu_bo_va_mapping *mapping;

	int r;
@@ -1590,11 +1595,10 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 
	if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {

		(*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;

		amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);

		r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false,

				    false);

		r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);

		if (r)

			return r;

	}



	return amdgpu_ttm_bind(&(*bo)->tbo, &(*bo)->tbo.mem);

	return amdgpu_ttm_alloc_gart(&(*bo)->tbo);

}