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Commit 9bebf348 authored by Bartlomiej Zolnierkiewicz's avatar Bartlomiej Zolnierkiewicz Committed by Eduardo Valentin
Browse files

thermal: ti-soc-thermal: remove dead code 



Majority of this code (i.e. functions from ti-bandgap.c) has been
introduced in May 2013 by commit eb982001 ("thermal: introduce TI
SoC thermal driver"). Just remove it altogether (in case it is needed
it can be easily resurrected from git repo).

While at it fix incorrect "not used" comments.

Tested-by: default avatarKeerthy <j-keerthy@ti.com>
Acked-by: default avatarKeerthy <j-keerthy@ti.com>
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: default avatarEduardo Valentin <edubezval@gmail.com>
parent be926cee

drivers/thermal/ti-soc-thermal/dra752-bandgap.h

+0 −68
Original line number Diff line number Diff line
@@ -54,56 +54,36 @@ 
#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET		0x8

#define DRA752_TEMP_SENSOR_CORE_OFFSET			0x154

#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET		0x1ac

#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET		0x1c4

#define DRA752_DTEMP_CORE_0_OFFSET			0x208

#define DRA752_DTEMP_CORE_1_OFFSET			0x20c

#define DRA752_DTEMP_CORE_2_OFFSET			0x210

#define DRA752_DTEMP_CORE_3_OFFSET			0x214

#define DRA752_DTEMP_CORE_4_OFFSET			0x218



/* DRA752.iva register offsets */

#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET		0x388

#define DRA752_TEMP_SENSOR_IVA_OFFSET			0x398

#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET		0x3a4

#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET		0x3b4

#define DRA752_DTEMP_IVA_0_OFFSET			0x3d0

#define DRA752_DTEMP_IVA_1_OFFSET			0x3d4

#define DRA752_DTEMP_IVA_2_OFFSET			0x3d8

#define DRA752_DTEMP_IVA_3_OFFSET			0x3dc

#define DRA752_DTEMP_IVA_4_OFFSET			0x3e0



/* DRA752.mpu register offsets */

#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET		0x4

#define DRA752_TEMP_SENSOR_MPU_OFFSET			0x14c

#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET		0x1a4

#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET		0x1bc

#define DRA752_DTEMP_MPU_0_OFFSET			0x1e0

#define DRA752_DTEMP_MPU_1_OFFSET			0x1e4

#define DRA752_DTEMP_MPU_2_OFFSET			0x1e8

#define DRA752_DTEMP_MPU_3_OFFSET			0x1ec

#define DRA752_DTEMP_MPU_4_OFFSET			0x1f0



/* DRA752.dspeve register offsets */

#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET			0x384

#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET			0x394

#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET			0x3a0

#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET		0x3b0

#define DRA752_DTEMP_DSPEVE_0_OFFSET				0x3bc

#define DRA752_DTEMP_DSPEVE_1_OFFSET				0x3c0

#define DRA752_DTEMP_DSPEVE_2_OFFSET				0x3c4

#define DRA752_DTEMP_DSPEVE_3_OFFSET				0x3c8

#define DRA752_DTEMP_DSPEVE_4_OFFSET				0x3cc



/* DRA752.gpu register offsets */

#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET		0x0

#define DRA752_TEMP_SENSOR_GPU_OFFSET			0x150

#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET		0x1a8

#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET		0x1c0

#define DRA752_DTEMP_GPU_0_OFFSET			0x1f4

#define DRA752_DTEMP_GPU_1_OFFSET			0x1f8

#define DRA752_DTEMP_GPU_2_OFFSET			0x1fc

#define DRA752_DTEMP_GPU_3_OFFSET			0x200

#define DRA752_DTEMP_GPU_4_OFFSET			0x204



/**

 * Register bitfields for DRA752
@@ -114,7 +94,6 @@ 
 */



/* DRA752.BANDGAP_STATUS_1 */

#define DRA752_BANDGAP_STATUS_1_ALERT_MASK		BIT(31)

#define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK		BIT(5)

#define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK		BIT(4)

#define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK		BIT(3)
@@ -125,10 +104,6 @@ 
/* DRA752.BANDGAP_CTRL_2 */

#define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK			BIT(22)

#define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK		BIT(21)

#define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK			BIT(19)

#define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK			BIT(18)

#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK		BIT(16)

#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK		BIT(15)

#define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK			BIT(3)

#define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK		BIT(2)

#define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK		BIT(1)
@@ -141,17 +116,10 @@ 
#define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK		BIT(0)



/* DRA752.BANDGAP_CTRL_1 */

#define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK			(0x3 << 30)

#define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK		(0x7 << 27)

#define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK			BIT(23)

#define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK			BIT(22)

#define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK			BIT(21)

#define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK			BIT(20)

#define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK			BIT(19)

#define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK			BIT(18)

#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK		BIT(17)

#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK		BIT(16)

#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK		BIT(15)

#define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK		BIT(5)

#define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK		BIT(4)

#define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK			BIT(3)
@@ -168,22 +136,6 @@ 
#define DRA752_BANDGAP_THRESHOLD_HOT_MASK		(0x3ff << 16)

#define DRA752_BANDGAP_THRESHOLD_COLD_MASK		(0x3ff << 0)





/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */

#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK		(0xffffffff << 0)



/* DRA752.BANDGAP_CUMUL_DTEMP_IVA */

#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK		(0xffffffff << 0)



/* DRA752.BANDGAP_CUMUL_DTEMP_MPU */

#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK		(0xffffffff << 0)



/* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */

#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK		(0xffffffff << 0)



/* DRA752.BANDGAP_CUMUL_DTEMP_GPU */

#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK		(0xffffffff << 0)



/**

 * Temperature limits and thresholds for DRA752

 *
@@ -202,10 +154,6 @@ 
/* bandgap clock limits */

#define DRA752_GPU_MAX_FREQ				1500000

#define DRA752_GPU_MIN_FREQ				1000000

/* sensor limits */

#define DRA752_GPU_MIN_TEMP				-40000

#define DRA752_GPU_MAX_TEMP				125000

#define DRA752_GPU_HYST_VAL				5000

/* interrupts thresholds */

#define DRA752_GPU_T_HOT				800

#define DRA752_GPU_T_COLD				795
@@ -214,10 +162,6 @@ 
/* bandgap clock limits */

#define DRA752_MPU_MAX_FREQ				1500000

#define DRA752_MPU_MIN_FREQ				1000000

/* sensor limits */

#define DRA752_MPU_MIN_TEMP				-40000

#define DRA752_MPU_MAX_TEMP				125000

#define DRA752_MPU_HYST_VAL				5000

/* interrupts thresholds */

#define DRA752_MPU_T_HOT				800

#define DRA752_MPU_T_COLD				795
@@ -226,10 +170,6 @@ 
/* bandgap clock limits */

#define DRA752_CORE_MAX_FREQ				1500000

#define DRA752_CORE_MIN_FREQ				1000000

/* sensor limits */

#define DRA752_CORE_MIN_TEMP				-40000

#define DRA752_CORE_MAX_TEMP				125000

#define DRA752_CORE_HYST_VAL				5000

/* interrupts thresholds */

#define DRA752_CORE_T_HOT				800

#define DRA752_CORE_T_COLD				795
@@ -238,10 +178,6 @@ 
/* bandgap clock limits */

#define DRA752_DSPEVE_MAX_FREQ				1500000

#define DRA752_DSPEVE_MIN_FREQ				1000000

/* sensor limits */

#define DRA752_DSPEVE_MIN_TEMP				-40000

#define DRA752_DSPEVE_MAX_TEMP				125000

#define DRA752_DSPEVE_HYST_VAL				5000

/* interrupts thresholds */

#define DRA752_DSPEVE_T_HOT				800

#define DRA752_DSPEVE_T_COLD				795
@@ -250,10 +186,6 @@ 
/* bandgap clock limits */

#define DRA752_IVA_MAX_FREQ				1500000

#define DRA752_IVA_MIN_FREQ				1000000

/* sensor limits */

#define DRA752_IVA_MIN_TEMP				-40000

#define DRA752_IVA_MAX_TEMP				125000

#define DRA752_IVA_HYST_VAL				5000

/* interrupts thresholds */

#define DRA752_IVA_T_HOT				800

#define DRA752_IVA_T_COLD				795

drivers/thermal/ti-soc-thermal/dra752-thermal-data.c

+0 −65
Original line number Diff line number Diff line
@@ -41,24 +41,16 @@ dra752_core_temp_sensor_registers = { 
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,

	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,

	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,

	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,

	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,

	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,

	.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,

	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,

	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,

	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,

	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,

	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,

	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,

	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,

	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,

	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,

	.ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,

	.ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,

	.ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,

	.ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,

	.ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,

	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,

};
@@ -74,24 +66,16 @@ dra752_iva_temp_sensor_registers = { 
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,

	.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,

	.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,

	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,

	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,

	.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,

	.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,

	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,

	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,

	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,

	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,

	.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,

	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,

	.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,

	.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,

	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,

	.ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,

	.ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,

	.ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,

	.ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,

	.ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,

	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,

};
@@ -107,24 +91,16 @@ dra752_mpu_temp_sensor_registers = { 
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,

	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,

	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,

	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,

	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,

	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,

	.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,

	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,

	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,

	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,

	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,

	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,

	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,

	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,

	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,

	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,

	.ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,

	.ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,

	.ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,

	.ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,

	.ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,

	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,

};
@@ -140,24 +116,16 @@ dra752_dspeve_temp_sensor_registers = { 
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,

	.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,

	.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,

	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,

	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,

	.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,

	.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,

	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,

	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,

	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,

	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,

	.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,

	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,

	.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,

	.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,

	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,

	.ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,

	.ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,

	.ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,

	.ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,

	.ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,

	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,

};
@@ -173,24 +141,16 @@ dra752_gpu_temp_sensor_registers = { 
	.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,

	.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,

	.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,

	.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,

	.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,

	.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,

	.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,

	.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,

	.bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,

	.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,

	.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,

	.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,

	.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,

	.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,

	.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,

	.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET,

	.ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET,

	.ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,

	.ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,

	.ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET,

	.ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET,

	.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,

};
@@ -200,11 +160,6 @@ static struct temp_sensor_data dra752_mpu_temp_sensor_data = { 
	.t_cold = DRA752_MPU_T_COLD,

	.min_freq = DRA752_MPU_MIN_FREQ,

	.max_freq = DRA752_MPU_MAX_FREQ,

	.max_temp = DRA752_MPU_MAX_TEMP,

	.min_temp = DRA752_MPU_MIN_TEMP,

	.hyst_val = DRA752_MPU_HYST_VAL,

	.update_int1 = 1000,

	.update_int2 = 2000,

};



/* Thresholds and limits for DRA752 GPU temperature sensor */
@@ -213,11 +168,6 @@ static struct temp_sensor_data dra752_gpu_temp_sensor_data = { 
	.t_cold = DRA752_GPU_T_COLD,

	.min_freq = DRA752_GPU_MIN_FREQ,

	.max_freq = DRA752_GPU_MAX_FREQ,

	.max_temp = DRA752_GPU_MAX_TEMP,

	.min_temp = DRA752_GPU_MIN_TEMP,

	.hyst_val = DRA752_GPU_HYST_VAL,

	.update_int1 = 1000,

	.update_int2 = 2000,

};



/* Thresholds and limits for DRA752 CORE temperature sensor */
@@ -226,11 +176,6 @@ static struct temp_sensor_data dra752_core_temp_sensor_data = { 
	.t_cold = DRA752_CORE_T_COLD,

	.min_freq = DRA752_CORE_MIN_FREQ,

	.max_freq = DRA752_CORE_MAX_FREQ,

	.max_temp = DRA752_CORE_MAX_TEMP,

	.min_temp = DRA752_CORE_MIN_TEMP,

	.hyst_val = DRA752_CORE_HYST_VAL,

	.update_int1 = 1000,

	.update_int2 = 2000,

};



/* Thresholds and limits for DRA752 DSPEVE temperature sensor */
@@ -239,11 +184,6 @@ static struct temp_sensor_data dra752_dspeve_temp_sensor_data = { 
	.t_cold = DRA752_DSPEVE_T_COLD,

	.min_freq = DRA752_DSPEVE_MIN_FREQ,

	.max_freq = DRA752_DSPEVE_MAX_FREQ,

	.max_temp = DRA752_DSPEVE_MAX_TEMP,

	.min_temp = DRA752_DSPEVE_MIN_TEMP,

	.hyst_val = DRA752_DSPEVE_HYST_VAL,

	.update_int1 = 1000,

	.update_int2 = 2000,

};



/* Thresholds and limits for DRA752 IVA temperature sensor */
@@ -252,11 +192,6 @@ static struct temp_sensor_data dra752_iva_temp_sensor_data = { 
	.t_cold = DRA752_IVA_T_COLD,

	.min_freq = DRA752_IVA_MIN_FREQ,

	.max_freq = DRA752_IVA_MAX_FREQ,

	.max_temp = DRA752_IVA_MAX_TEMP,

	.min_temp = DRA752_IVA_MIN_TEMP,

	.hyst_val = DRA752_IVA_HYST_VAL,

	.update_int1 = 1000,

	.update_int2 = 2000,

};



/*

drivers/thermal/ti-soc-thermal/omap3-thermal-data.c

+0 −6
Original line number Diff line number Diff line
@@ -48,9 +48,6 @@ omap34xx_mpu_temp_sensor_registers = { 
static struct temp_sensor_data omap34xx_mpu_temp_sensor_data = {

	.min_freq = 32768,

	.max_freq = 32768,

	.max_temp = 125000,

	.min_temp = -40000,

	.hyst_val = 5000,

};



/*
@@ -119,9 +116,6 @@ omap36xx_mpu_temp_sensor_registers = { 
static struct temp_sensor_data omap36xx_mpu_temp_sensor_data = {

	.min_freq = 32768,

	.max_freq = 32768,

	.max_temp = 125000,

	.min_temp = -40000,

	.hyst_val = 5000,

};



/*

drivers/thermal/ti-soc-thermal/omap4-thermal-data.c

+0 −10
Original line number Diff line number Diff line
@@ -42,9 +42,6 @@ omap4430_mpu_temp_sensor_registers = { 
static struct temp_sensor_data omap4430_mpu_temp_sensor_data = {

	.min_freq = OMAP4430_MIN_FREQ,

	.max_freq = OMAP4430_MAX_FREQ,

	.max_temp = OMAP4430_MAX_TEMP,

	.min_temp = OMAP4430_MIN_TEMP,

	.hyst_val = OMAP4430_HYST_VAL,

};



/*
@@ -121,8 +118,6 @@ omap4460_mpu_temp_sensor_registers = { 
	.tshut_cold_mask = OMAP4460_TSHUT_COLD_MASK,



	.bgap_status = OMAP4460_BGAP_STATUS_OFFSET,

	.status_clean_stop_mask = OMAP4460_CLEAN_STOP_MASK,

	.status_bgap_alert_mask = OMAP4460_BGAP_ALERT_MASK,

	.status_hot_mask = OMAP4460_HOT_FLAG_MASK,

	.status_cold_mask = OMAP4460_COLD_FLAG_MASK,
@@ -137,11 +132,6 @@ static struct temp_sensor_data omap4460_mpu_temp_sensor_data = { 
	.t_cold = OMAP4460_T_COLD,

	.min_freq = OMAP4460_MIN_FREQ,

	.max_freq = OMAP4460_MAX_FREQ,

	.max_temp = OMAP4460_MAX_TEMP,

	.min_temp = OMAP4460_MIN_TEMP,

	.hyst_val = OMAP4460_HYST_VAL,

	.update_int1 = 1000,

	.update_int2 = 2000,

};



/*

drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h

+0 −10
Original line number Diff line number Diff line
@@ -73,10 +73,6 @@ 
/* bandgap clock limits (no control on 4430) */

#define OMAP4430_MAX_FREQ				32768

#define OMAP4430_MIN_FREQ				32768

/* sensor limits */

#define OMAP4430_MIN_TEMP				-40000

#define OMAP4430_MAX_TEMP				125000

#define OMAP4430_HYST_VAL				5000



/**

 * *** OMAP4460 *** Applicable for OMAP4470
@@ -143,8 +139,6 @@ 
#define OMAP4460_TSHUT_COLD_MASK			(0x3ff << 0)



/* OMAP4460.BANDGAP_STATUS bits */

#define OMAP4460_CLEAN_STOP_MASK			BIT(3)

#define OMAP4460_BGAP_ALERT_MASK			BIT(2)

#define OMAP4460_HOT_FLAG_MASK				BIT(1)

#define OMAP4460_COLD_FLAG_MASK				BIT(0)
@@ -162,10 +156,6 @@ 
/* bandgap clock limits */

#define OMAP4460_MAX_FREQ				1500000

#define OMAP4460_MIN_FREQ				1000000

/* sensor limits */

#define OMAP4460_MIN_TEMP				-40000

#define OMAP4460_MAX_TEMP				123000

#define OMAP4460_HYST_VAL				5000

/* interrupts thresholds */

#define OMAP4460_TSHUT_HOT				900	/* 122 deg C */

#define OMAP4460_TSHUT_COLD				895	/* 100 deg C */