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Commit 9be712ef authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm/tegra/for-4.16-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-next 

drm/tegra: Changes for v4.16-rc1

The bulk of these changes are preparation work and addition of support
for Tegra186. Currently only HDMI output (the primary output on Jetson
TX2) is supported, but the hardware is also capable of doing DSI and
DisplayPort.

Tegra DRM now also uses the atomic commit helpers instead of the open-
coded variant that was only doing half its job. As a bit of a byproduct
of the Tegra186 support the driver also gained HDMI 2.0 as well as zpos
property support.

Along the way there are also a few patches to clean up a few things and
fix minor issues.

* tag 'drm/tegra/for-4.16-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux: (51 commits)
  drm/tegra: dc: Properly cleanup overlay planes
  drm/tegra: dc: Fix possible_crtcs mask for planes
  drm/tegra: dc: Restore YUV overlay support
  drm/tegra: dc: Implement legacy blending
  drm/tegra: Correct timeout in tegra_syncpt_wait
  drm/tegra: gem: Correct iommu_map_sg() error checking
  drm/tegra: dc: Link DC1 to DC0 on Tegra20
  drm/tegra: Fix non-debugfs builds
  drm/tegra: dpaux: Keep reset defaults for hybrid pad parameters
  drm/tegra: Mark Tegra186 display hub PM functions __maybe_unused
  drm/tegra: Use IOMMU groups
  gpu: host1x: Use IOMMU groups
  drm/tegra: Implement zpos property
  drm/tegra: dc: Remove redundant spinlock
  drm/tegra: dc: Use direct offset to plane registers
  drm/tegra: dc: Support more formats
  drm/tegra: fb: Force alpha formats
  drm/tegra: dpaux: Add Tegra186 support
  drm/tegra: dpaux: Implement runtime PM
  drm/tegra: sor: Support HDMI 2.0 modes
  ...
parents 323b20c4 8f62142e

Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt

+13 −1
Original line number Diff line number Diff line
@@ -206,21 +206,33 @@ of the following host1x client modules: 
    - "nvidia,tegra132-sor": for Tegra132

    - "nvidia,tegra210-sor": for Tegra210

    - "nvidia,tegra210-sor1": for Tegra210

    - "nvidia,tegra186-sor": for Tegra186

    - "nvidia,tegra186-sor1": for Tegra186

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain an entry for each entry in clock-names.

    See ../clocks/clock-bindings.txt for details.

  - clock-names: Must include the following entries:

    - sor: clock input for the SOR hardware

    - source: source clock for the SOR clock

    - out: SOR output clock

    - parent: input for the pixel clock

    - dp: reference clock for the SOR clock

    - safe: safe reference for the SOR clock during power up



    For Tegra186 and later:

    - pad: SOR pad output clock (on Tegra186 and later)



    Obsolete:

    - source: source clock for the SOR clock (obsolete, use "out" instead)



  - resets: Must contain an entry for each entry in reset-names.

    See ../reset/reset.txt for details.

  - reset-names: Must include the following entries:

    - sor



  Required properties on Tegra186 and later:

  - nvidia,interface: index of the SOR interface



  Optional properties:

  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection

drivers/gpu/drm/tegra/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ tegra-drm-y := \ 
	drm.o \

	gem.o \

	fb.o \

	hub.o \

	plane.o \

	dc.o \

	output.o \

	rgb.o \