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Commit 9b70afd9 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Kukjin Kim
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ARM: dts: Use labels for overriding nodes in exynos4210-trats



Usage of labels instead of full paths reduces possible mistakes when
overriding nodes.

Signed-off-by: default avatarKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: default avatarKukjin Kim <kgene@kernel.org>
parent bad0b9c9
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+296 −296
Original line number Diff line number Diff line
@@ -89,42 +89,6 @@
		};
	};

	hsotg@12480000 {
		vusb_d-supply = <&vusb_reg>;
		vusb_a-supply = <&vusbdac_reg>;
		dr_mode = "peripheral";
		status = "okay";
	};

	sdhci_emmc: sdhci@12510000 {
		bus-width = <8>;
		non-removable;
		pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
		pinctrl-names = "default";
		vmmc-supply = <&vemmc_reg>;
		status = "okay";
	};

	exynos-usbphy@125B0000 {
		status = "okay";
	};

	serial@13800000 {
		status = "okay";
	};

	serial@13810000 {
		status = "okay";
	};

	serial@13820000 {
		status = "okay";
	};

	serial@13830000 {
		status = "okay";
	};

	gpio-keys {
		compatible = "gpio-keys";

@@ -158,7 +122,145 @@
		};
	};

	i2c@13890000 {
	fixed-rate-clocks {
		xxti {
			compatible = "samsung,clock-xxti";
			clock-frequency = <0>;
		};

		xusbxti {
			compatible = "samsung,clock-xusbxti";
			clock-frequency = <24000000>;
		};
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			cooling-maps {
				map0 {
				     /* Corresponds to 800MHz at freq_table */
				     cooling-device = <&cpu0 2 2>;
				};
				map1 {
				     /* Corresponds to 200MHz at freq_table */
				     cooling-device = <&cpu0 4 4>;
			       };
		       };
		};
	};

	camera {
		pinctrl-names = "default";
		pinctrl-0 = <>;
		status = "okay";

		fimc_0: fimc@11800000 {
			status = "okay";
			assigned-clocks = <&clock CLK_MOUT_FIMC0>,
					<&clock CLK_SCLK_FIMC0>;
			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
			assigned-clock-rates = <0>, <160000000>;
		};

		fimc_1: fimc@11810000 {
			status = "okay";
			assigned-clocks = <&clock CLK_MOUT_FIMC1>,
					<&clock CLK_SCLK_FIMC1>;
			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
			assigned-clock-rates = <0>, <160000000>;
		};

		fimc_2: fimc@11820000 {
			status = "okay";
			assigned-clocks = <&clock CLK_MOUT_FIMC2>,
					<&clock CLK_SCLK_FIMC2>;
			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
			assigned-clock-rates = <0>, <160000000>;
		};

		fimc_3: fimc@11830000 {
			status = "okay";
			assigned-clocks = <&clock CLK_MOUT_FIMC3>,
					<&clock CLK_SCLK_FIMC3>;
			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
			assigned-clock-rates = <0>, <160000000>;
		};
	};
};

&dsi_0 {
	vddcore-supply = <&vusb_reg>;
	vddio-supply = <&vmipi_reg>;
	samsung,pll-clock-frequency = <24000000>;
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@1 {
			reg = <1>;

			dsi_out: endpoint {
				remote-endpoint = <&dsi_in>;
				samsung,burst-clock-frequency = <500000000>;
				samsung,esc-clock-frequency = <20000000>;
			};
		};
	};

	panel@0 {
		reg = <0>;
		compatible = "samsung,s6e8aa0";
		vdd3-supply = <&vcclcd_reg>;
		vci-supply = <&vlcd_reg>;
		reset-gpios = <&gpy4 5 0>;
		power-on-delay= <50>;
		reset-delay = <100>;
		init-delay = <100>;
		flip-horizontal;
		flip-vertical;
		panel-width-mm = <58>;
		panel-height-mm = <103>;

		display-timings {
			timing-0 {
				clock-frequency = <57153600>;
				hactive = <720>;
				vactive = <1280>;
				hfront-porch = <5>;
				hback-porch = <5>;
				hsync-len = <5>;
				vfront-porch = <13>;
				vback-porch = <1>;
				vsync-len = <2>;
			};
		};

		port {
			dsi_in: endpoint {
				remote-endpoint = <&dsi_out>;
			};
		};
	};
};

&exynos_usbphy {
	status = "okay";
};

&fimd {
	status = "okay";
};

&hsotg {
	vusb_d-supply = <&vusb_reg>;
	vusb_a-supply = <&vusbdac_reg>;
	dr_mode = "peripheral";
	status = "okay";
};

&i2c_3 {
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-slave-addr = <0x10>;
	samsung,i2c-max-bus-freq = <400000>;
@@ -178,7 +280,7 @@
	};
};

	i2c@138B0000 {
&i2c_5 {
	samsung,i2c-sda-delay = <100>;
	samsung,i2c-slave-addr = <0x10>;
	samsung,i2c-max-bus-freq = <100000>;
@@ -353,133 +455,31 @@
	};
};

	fixed-rate-clocks {
		xxti {
			compatible = "samsung,clock-xxti";
			clock-frequency = <0>;
		};

		xusbxti {
			compatible = "samsung,clock-xusbxti";
			clock-frequency = <24000000>;
		};
	};

	dsi_0: dsi@11C80000 {
		vddcore-supply = <&vusb_reg>;
		vddio-supply = <&vmipi_reg>;
		samsung,pll-clock-frequency = <24000000>;
		status = "okay";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;

				dsi_out: endpoint {
					remote-endpoint = <&dsi_in>;
					samsung,burst-clock-frequency = <500000000>;
					samsung,esc-clock-frequency = <20000000>;
				};
			};
		};

		panel@0 {
			reg = <0>;
			compatible = "samsung,s6e8aa0";
			vdd3-supply = <&vcclcd_reg>;
			vci-supply = <&vlcd_reg>;
			reset-gpios = <&gpy4 5 0>;
			power-on-delay= <50>;
			reset-delay = <100>;
			init-delay = <100>;
			flip-horizontal;
			flip-vertical;
			panel-width-mm = <58>;
			panel-height-mm = <103>;

			display-timings {
				timing-0 {
					clock-frequency = <57153600>;
					hactive = <720>;
					vactive = <1280>;
					hfront-porch = <5>;
					hback-porch = <5>;
					hsync-len = <5>;
					vfront-porch = <13>;
					vback-porch = <1>;
					vsync-len = <2>;
				};
			};

			port {
				dsi_in: endpoint {
					remote-endpoint = <&dsi_out>;
				};
			};
		};
	};

	fimd@11c00000 {
&sdhci_0 {
	bus-width = <8>;
	non-removable;
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
	pinctrl-names = "default";
	vmmc-supply = <&vemmc_reg>;
	status = "okay";
};

	tmu@100C0000 {
&serial_0 {
	status = "okay";
};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			cooling-maps {
				map0 {
				     /* Corresponds to 800MHz at freq_table */
				     cooling-device = <&cpu0 2 2>;
				};
				map1 {
				     /* Corresponds to 200MHz at freq_table */
				     cooling-device = <&cpu0 4 4>;
			       };
		       };
		};
	};

	camera {
		pinctrl-names = "default";
		pinctrl-0 = <>;
		status = "okay";

		fimc_0: fimc@11800000 {
&serial_1 {
	status = "okay";
			assigned-clocks = <&clock CLK_MOUT_FIMC0>,
					<&clock CLK_SCLK_FIMC0>;
			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
			assigned-clock-rates = <0>, <160000000>;
};

		fimc_1: fimc@11810000 {
&serial_2 {
	status = "okay";
			assigned-clocks = <&clock CLK_MOUT_FIMC1>,
					<&clock CLK_SCLK_FIMC1>;
			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
			assigned-clock-rates = <0>, <160000000>;
};

		fimc_2: fimc@11820000 {
&serial_3 {
	status = "okay";
			assigned-clocks = <&clock CLK_MOUT_FIMC2>,
					<&clock CLK_SCLK_FIMC2>;
			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
			assigned-clock-rates = <0>, <160000000>;
};

		fimc_3: fimc@11830000 {
&tmu {
	status = "okay";
			assigned-clocks = <&clock CLK_MOUT_FIMC3>,
					<&clock CLK_SCLK_FIMC3>;
			assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
			assigned-clock-rates = <0>, <160000000>;
		};
	};
};