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Commit 9b54470a authored by Stafford Horne's avatar Stafford Horne
Browse files

irqchip: add initial support for ompic 

IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
described in the Multi-core support section of the OpenRISC 1.2
architecture specification:

  https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf



Each OpenRISC core contains a full interrupt controller which is used in
the SMP architecture for interrupt balancing.  This IPI device, the
ompic, is the only external device required for enabling SMP on
OpenRISC.

Pending ops are stored in a memory bit mask which can allow multiple
pending operations to be set and serviced at a time. This is mostly
borrowed from the alpha IPI implementation.

Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: converted ops to bitmask, wrote commit message]
Signed-off-by: default avatarStafford Horne <shorne@gmail.com>
parent fab8be88

Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt

0 → 100644
+22 −0
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Open Multi-Processor Interrupt Controller



Required properties:



- compatible : This should be "openrisc,ompic"

- reg : Specifies base physical address and size of the register space. The

  size is based on the number of cores the controller has been configured

  to handle, this should be set to 8 bytes per cpu core.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : This should be set to 0 as this will not be an irq

  parent.

- interrupts : Specifies the interrupt line to which the ompic is wired.



Example:



ompic: interrupt-controller@98000000 {

	compatible = "openrisc,ompic";

	reg = <0x98000000 16>;

	interrupt-controller;

	#interrupt-cells = <0>;

	interrupts = <1>;

};

MAINTAINERS

+1 −0
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@@ -10034,6 +10034,7 @@ S: Maintained 
F:	Documentation/devicetree/bindings/openrisc/

F:	Documentation/openrisc/

F:	arch/openrisc/

F:	drivers/irqchip/irq-ompic.c

F:	drivers/irqchip/irq-or1k-*



OPENVSWITCH

arch/openrisc/Kconfig

+1 −0
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@@ -30,6 +30,7 @@ config OPENRISC 
	select NO_BOOTMEM

	select ARCH_USE_QUEUED_SPINLOCKS

	select ARCH_USE_QUEUED_RWLOCKS

	select OMPIC if SMP



config CPU_BIG_ENDIAN

	def_bool y

drivers/irqchip/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -151,6 +151,9 @@ config CLPS711X_IRQCHIP 
	select SPARSE_IRQ

	default y



config OMPIC

	bool



config OR1K_PIC

	bool

	select IRQ_DOMAIN

drivers/irqchip/Makefile

+1 −0
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@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o 
obj-$(CONFIG_METAG)			+= irq-metag-ext.o

obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o

obj-$(CONFIG_CLPS711X_IRQCHIP)		+= irq-clps711x.o

obj-$(CONFIG_OMPIC)			+= irq-ompic.o

obj-$(CONFIG_OR1K_PIC)			+= irq-or1k-pic.o

obj-$(CONFIG_ORION_IRQCHIP)		+= irq-orion.o

obj-$(CONFIG_OMAP_IRQCHIP)		+= irq-omap-intc.o