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Commit 9adda353 authored by Yixun Lan's avatar Yixun Lan Committed by Kevin Hilman
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ARM64: dts: meson: fix clock source of the pclk for UART_AO 



>From the hardware perspective, the actual pclk of the AO uarts
is the corresponding clkc_ao uart gate, not the main clock controller clk81.
This was not problem so far, because the uart_gate had
the CLK_IGNORE_UNUSED flag, which kept the gate open.

We plan to remove the CLK_IGNORE_UNUSED flag in another patch,
but before doing that, we need to fix the clock in the DTS file.

Signed-off-by: default avatarYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent e03421ec

arch/arm64/boot/dts/amlogic/meson-axg.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -1174,7 +1174,7 @@ 
				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";

				reg = <0x0 0x3000 0x0 0x18>;

				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;

				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;

				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;

				clock-names = "xtal", "pclk", "baud";

				status = "disabled";

			};
@@ -1183,7 +1183,7 @@ 
				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";

				reg = <0x0 0x4000 0x0 0x18>;

				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;

				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;

				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;

				clock-names = "xtal", "pclk", "baud";

				status = "disabled";

			};

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -751,12 +751,12 @@ 
};



&uart_AO {

	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;

	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;

	clock-names = "xtal", "pclk", "baud";

};



&uart_AO_B {

	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;

	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;

	clock-names = "xtal", "pclk", "baud";

};

arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -760,12 +760,12 @@ 
};



&uart_AO {

	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;

	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;

	clock-names = "xtal", "pclk", "baud";

};



&uart_AO_B {

	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;

	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;

	clock-names = "xtal", "pclk", "baud";

};