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Commit 9aa49ea3 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k_hw: Rename antenna diversity macros 



The register macros for antenna diversity are common for
AR9462 and AR9565, rename them.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent b7f59766

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

+12 −15
Original line number Diff line number Diff line
@@ -3627,19 +3627,16 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 
		regval &= (~AR_ANT_DIV_CTRL_ALL);

		regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;

		/* enable_lnadiv */

		regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);

		regval |= ((value >> 6) & 0x1) <<

				AR_PHY_9485_ANT_DIV_LNADIV_S;

		regval &= (~AR_PHY_ANT_DIV_LNADIV);

		regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;

		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);



		/*enable fast_div */

		regval = REG_READ(ah, AR_PHY_CCK_DETECT);

		regval &= (~AR_FAST_DIV_ENABLE);

		regval |= ((value >> 7) & 0x1) <<

				AR_FAST_DIV_ENABLE_S;

		regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;

		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);

		ant_div_ctl1 =

			ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);

		ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);

		/* check whether antenna diversity is enabled */

		if ((ant_div_ctl1 >> 0x6) == 0x3) {

			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
@@ -3647,15 +3644,15 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 
			 * clear bits 25-30 main_lnaconf, alt_lnaconf,

			 * main_tb, alt_tb

			 */

			regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |

					AR_PHY_9485_ANT_DIV_ALT_LNACONF |

					AR_PHY_9485_ANT_DIV_ALT_GAINTB |

					AR_PHY_9485_ANT_DIV_MAIN_GAINTB));

			regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |

				     AR_PHY_ANT_DIV_ALT_LNACONF |

				     AR_PHY_ANT_DIV_ALT_GAINTB |

				     AR_PHY_ANT_DIV_MAIN_GAINTB));

			/* by default use LNA1 for the main antenna */

			regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<

					AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);

			regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<

					AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);

			regval |= (AR_PHY_ANT_DIV_LNA1 <<

				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);

			regval |= (AR_PHY_ANT_DIV_LNA2 <<

				   AR_PHY_ANT_DIV_ALT_LNACONF_S);

			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

		}

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+22 −23
Original line number Diff line number Diff line
@@ -1281,12 +1281,12 @@ static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, 
	u32 regval;



	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

	antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>

				  AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;

	antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>

				 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;

	antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>

				  AR_PHY_9485_ANT_FAST_DIV_BIAS_S;

	antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>

				  AR_PHY_ANT_DIV_MAIN_LNACONF_S;

	antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>

				 AR_PHY_ANT_DIV_ALT_LNACONF_S;

	antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>

				  AR_PHY_ANT_FAST_DIV_BIAS_S;



	if (AR_SREV_9330_11(ah)) {

		antconf->lna1_lna2_delta = -9;
@@ -1306,22 +1306,21 @@ static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, 
	u32 regval;



	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

	regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |

		    AR_PHY_9485_ANT_DIV_ALT_LNACONF |

		    AR_PHY_9485_ANT_FAST_DIV_BIAS |

		    AR_PHY_9485_ANT_DIV_MAIN_GAINTB |

		    AR_PHY_9485_ANT_DIV_ALT_GAINTB);

	regval |= ((antconf->main_lna_conf <<

					AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)

		   & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);

	regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)

		   & AR_PHY_9485_ANT_DIV_ALT_LNACONF);

	regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)

		   & AR_PHY_9485_ANT_FAST_DIV_BIAS);

	regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)

		   & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);

	regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)

		   & AR_PHY_9485_ANT_DIV_ALT_GAINTB);

	regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |

		    AR_PHY_ANT_DIV_ALT_LNACONF |

		    AR_PHY_ANT_FAST_DIV_BIAS |

		    AR_PHY_ANT_DIV_MAIN_GAINTB |

		    AR_PHY_ANT_DIV_ALT_GAINTB);

	regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)

		   & AR_PHY_ANT_DIV_MAIN_LNACONF);

	regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)

		   & AR_PHY_ANT_DIV_ALT_LNACONF);

	regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)

		   & AR_PHY_ANT_FAST_DIV_BIAS);

	regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)

		   & AR_PHY_ANT_DIV_MAIN_GAINTB);

	regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)

		   & AR_PHY_ANT_DIV_ALT_GAINTB);



	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

}

drivers/net/wireless/ath/ath9k/ar9003_phy.h

+17 −17
Original line number Diff line number Diff line
@@ -280,23 +280,23 @@ 
#define AR_ANT_DIV_ENABLE_S	24





#define AR_PHY_9485_ANT_FAST_DIV_BIAS			0x00007e00

#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S                  9

#define AR_PHY_9485_ANT_DIV_LNADIV			0x01000000

#define AR_PHY_9485_ANT_DIV_LNADIV_S			24

#define AR_PHY_9485_ANT_DIV_ALT_LNACONF			0x06000000

#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S		25

#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF		0x18000000

#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S		27

#define AR_PHY_9485_ANT_DIV_ALT_GAINTB			0x20000000

#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S		29

#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB			0x40000000

#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S		30



#define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2		0x0

#define AR_PHY_9485_ANT_DIV_LNA2			0x1

#define AR_PHY_9485_ANT_DIV_LNA1			0x2

#define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2		0x3

#define AR_PHY_ANT_FAST_DIV_BIAS                0x00007e00

#define AR_PHY_ANT_FAST_DIV_BIAS_S              9

#define AR_PHY_ANT_DIV_LNADIV                   0x01000000

#define AR_PHY_ANT_DIV_LNADIV_S                 24

#define AR_PHY_ANT_DIV_ALT_LNACONF              0x06000000

#define AR_PHY_ANT_DIV_ALT_LNACONF_S            25

#define AR_PHY_ANT_DIV_MAIN_LNACONF             0x18000000

#define AR_PHY_ANT_DIV_MAIN_LNACONF_S           27

#define AR_PHY_ANT_DIV_ALT_GAINTB               0x20000000

#define AR_PHY_ANT_DIV_ALT_GAINTB_S             29

#define AR_PHY_ANT_DIV_MAIN_GAINTB              0x40000000

#define AR_PHY_ANT_DIV_MAIN_GAINTB_S            30



#define AR_PHY_ANT_DIV_LNA1_MINUS_LNA2          0x0

#define AR_PHY_ANT_DIV_LNA2                     0x1

#define AR_PHY_ANT_DIV_LNA1                     0x2

#define AR_PHY_ANT_DIV_LNA1_PLUS_LNA2           0x3



#define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)

#define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)