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Commit 99c59172 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/fb/gf100-: allocate mmu debug buffers



Later chipsets require setting this up both in FB and GR, so let's just
move the allocation to FB.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 917d95a8
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+3 −0
Original line number Diff line number Diff line
@@ -55,6 +55,9 @@ struct nvkm_fb {
		struct nvkm_fb_tile region[16];
		int regions;
	} tile;

	struct nvkm_memory *mmu_rd;
	struct nvkm_memory *mmu_wr;
};

bool nvkm_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
+4 −25
Original line number Diff line number Diff line
@@ -1616,30 +1616,10 @@ gf100_gr_oneinit(struct nvkm_gr *base)
{
	struct gf100_gr *gr = gf100_gr(base);
	struct nvkm_device *device = gr->base.engine.subdev.device;
	int ret, i, j;
	int i, j;

	nvkm_pmu_pgob(device->pmu, false);

	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false,
			      &gr->unk4188b4);
	if (ret)
		return ret;

	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false,
			      &gr->unk4188b8);
	if (ret)
		return ret;

	nvkm_kmap(gr->unk4188b4);
	for (i = 0; i < 0x1000; i += 4)
		nvkm_wo32(gr->unk4188b4, i, 0x00000010);
	nvkm_done(gr->unk4188b4);

	nvkm_kmap(gr->unk4188b8);
	for (i = 0; i < 0x1000; i += 4)
		nvkm_wo32(gr->unk4188b8, i, 0x00000010);
	nvkm_done(gr->unk4188b8);

	gr->rop_nr = gr->func->rops(gr);
	gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f;
	for (i = 0; i < gr->gpc_nr; i++) {
@@ -1736,8 +1716,6 @@ gf100_gr_dtor(struct nvkm_gr *base)
	gf100_gr_dtor_init(gr->fuc_sw_ctx);
	gf100_gr_dtor_init(gr->fuc_sw_nonctx);

	nvkm_memory_del(&gr->unk4188b8);
	nvkm_memory_del(&gr->unk4188b4);
	return gr;
}

@@ -1822,6 +1800,7 @@ int
gf100_gr_init(struct gf100_gr *gr)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fb *fb = device->fb;
	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
	u32 data[TPC_MAX / 8] = {};
	u8  tpcnr[GPC_MAX];
@@ -1834,8 +1813,8 @@ gf100_gr_init(struct gf100_gr *gr)
	nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);
	nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);
	nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8);
	nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8);

	gf100_gr_mmio(gr, gr->func->mmio);

+0 −3
Original line number Diff line number Diff line
@@ -101,9 +101,6 @@ struct gf100_gr {
	u8 ppc_mask[GPC_MAX];
	u8 ppc_tpc_nr[GPC_MAX][4];

	struct nvkm_memory *unk4188b4;
	struct nvkm_memory *unk4188b8;

	struct gf100_gr_data mmio_data[4];
	struct gf100_gr_mmio mmio_list[4096/8];
	u32  size;
+5 −2
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@
#include "gf100.h"
#include "ctxgf100.h"

#include <subdev/fb.h>

#include <nvif/class.h>

/*******************************************************************************
@@ -181,6 +183,7 @@ int
gk104_gr_init(struct gf100_gr *gr)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fb *fb = device->fb;
	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
	u32 data[TPC_MAX / 8] = {};
	u8  tpcnr[GPC_MAX];
@@ -193,8 +196,8 @@ gk104_gr_init(struct gf100_gr *gr)
	nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
	nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);
	nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);
	nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8);
	nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8);

	gf100_gr_mmio(gr, gr->func->mmio);

+4 −2
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@
#include "gf100.h"
#include "ctxgf100.h"

#include <subdev/fb.h>
#include <subdev/timer.h>

#include <nvif/class.h>
@@ -219,6 +220,7 @@ int
gk20a_gr_init(struct gf100_gr *gr)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	struct nvkm_fb *fb = device->fb;
	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
	u32 data[TPC_MAX / 8] = {};
	u8  tpcnr[GPC_MAX];
@@ -239,8 +241,8 @@ gk20a_gr_init(struct gf100_gr *gr)
		return ret;

	/* MMU debug buffer */
	nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8);
	nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8);
	nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(fb->mmu_wr) >> 8);
	nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(fb->mmu_rd) >> 8);

	if (gr->func->init_gpc_mmu)
		gr->func->init_gpc_mmu(gr);
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