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Commit 9953b72f authored by pding's avatar pding Committed by Alex Deucher
Browse files

drm/amdgpu: change redundant init logs to debug level 



When this VF stays in exclusive mode for long, other VFs will be
impacted.

The redundant messages causes exclusive mode timeout when they're
redirected. That is a normal use case for cloud service to redirect
guest log to virtual serial port.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarpding <Pixel.Ding@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bc1b1bf6

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 
		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();

		break;

	default:

		dev_info(adev->dev, "kfd not supported on this ASIC\n");

		dev_dbg(adev->dev, "kfd not supported on this ASIC\n");

		return;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

+4 −4
Original line number Diff line number Diff line
@@ -690,11 +690,11 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) 
			le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);

		/* set a reasonable default for DP */

		if (adev->clock.default_dispclk < 53900) {

			DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",

			DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n",

				  adev->clock.default_dispclk / 100);

			adev->clock.default_dispclk = 60000;

		} else if (adev->clock.default_dispclk <= 60000) {

			DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n",

			DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n",

				  adev->clock.default_dispclk / 100);

			adev->clock.default_dispclk = 62500;

		}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −3
Original line number Diff line number Diff line
@@ -1029,7 +1029,7 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev) 
		atom_card_info->ioreg_read = cail_ioreg_read;

		atom_card_info->ioreg_write = cail_ioreg_write;

	} else {

		DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");

		DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");

		atom_card_info->ioreg_read = cail_reg_read;

		atom_card_info->ioreg_write = cail_reg_write;

	}
@@ -2267,8 +2267,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
			dev_err(adev->dev, "gpu post error!\n");

			goto failed;

		}

	} else {

		DRM_INFO("GPU post is not needed\n");

	}



	if (adev->is_atom_fw) {

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+0 −1
Original line number Diff line number Diff line
@@ -306,7 +306,6 @@ MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled) 
module_param_named(cik_support, amdgpu_cik_support, int, 0444);

#endif





static const struct pci_device_id pciidlist[] = {

#ifdef  CONFIG_DRM_AMDGPU_SI

	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+3 −3
Original line number Diff line number Diff line
@@ -391,7 +391,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 
	ring->fence_drv.irq_type = irq_type;

	ring->fence_drv.initialized = true;



	dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "

	dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "

		"cpu addr 0x%p\n", ring->idx,

		ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);

	return 0;