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Commit 993feee9 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'qed-tunneling-offload'



Manish Chopra says:

====================
qed/qede: Add tunneling support

This patch series adds support for VXLAN, GRE and GENEVE tunnels
to be used over this driver. With this support, adapter can perform
TSO offload, inner/outer checksums offloads on TX and RX for
encapsulated packets.

V1->V2 [ Comments from Jesse Gross incorporated ]
* Drop general infrastructure change patch.
  "net: Make vxlan/geneve default udp ports public"
* Remove by default Linux default UDP ports configurations in driver.
  Instead, use general registration APIs for UDP port configurations
* Removing .ndo_features_check - we will add it later with proper change.

Please consider applying this series to net-next.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ee1c2797 14db81de
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+21 −0
Original line number Diff line number Diff line
@@ -103,4 +103,25 @@ config QEDE
	depends on QED
	---help---
	  This enables the support for ...

config QEDE_VXLAN
	bool "Virtual eXtensible Local Area Network support"
	default n
	depends on QEDE && VXLAN && !(QEDE=y && VXLAN=m)
	---help---
	  This enables hardware offload support for VXLAN protocol over
	  qede module. Say Y here if you want to enable hardware offload
	  support for Virtual eXtensible Local Area Network (VXLAN)
	  in the driver.

config QEDE_GENEVE
	bool "Generic Network Virtualization Encapsulation (GENEVE) support"
	depends on QEDE && GENEVE && !(QEDE=y && GENEVE=m)
	---help---
	  This allows one to create GENEVE virtual interfaces that provide
	  Layer 2 Networks over Layer 3 Networks. GENEVE is often used
	  to tunnel virtual network infrastructure in virtualized environments.
	  Say Y here if you want to enable hardware offload support for
	  Generic Network Virtualization Encapsulation (GENEVE) in the driver.

endif # NET_VENDOR_QLOGIC
+46 −0
Original line number Diff line number Diff line
@@ -74,6 +74,51 @@ struct qed_rt_data {
	bool	*b_valid;
};

enum qed_tunn_mode {
	QED_MODE_L2GENEVE_TUNN,
	QED_MODE_IPGENEVE_TUNN,
	QED_MODE_L2GRE_TUNN,
	QED_MODE_IPGRE_TUNN,
	QED_MODE_VXLAN_TUNN,
};

enum qed_tunn_clss {
	QED_TUNN_CLSS_MAC_VLAN,
	QED_TUNN_CLSS_MAC_VNI,
	QED_TUNN_CLSS_INNER_MAC_VLAN,
	QED_TUNN_CLSS_INNER_MAC_VNI,
	MAX_QED_TUNN_CLSS,
};

struct qed_tunn_start_params {
	unsigned long	tunn_mode;
	u16		vxlan_udp_port;
	u16		geneve_udp_port;
	u8		update_vxlan_udp_port;
	u8		update_geneve_udp_port;
	u8		tunn_clss_vxlan;
	u8		tunn_clss_l2geneve;
	u8		tunn_clss_ipgeneve;
	u8		tunn_clss_l2gre;
	u8		tunn_clss_ipgre;
};

struct qed_tunn_update_params {
	unsigned long	tunn_mode_update_mask;
	unsigned long	tunn_mode;
	u16		vxlan_udp_port;
	u16		geneve_udp_port;
	u8		update_rx_pf_clss;
	u8		update_tx_pf_clss;
	u8		update_vxlan_udp_port;
	u8		update_geneve_udp_port;
	u8		tunn_clss_vxlan;
	u8		tunn_clss_l2geneve;
	u8		tunn_clss_ipgeneve;
	u8		tunn_clss_l2gre;
	u8		tunn_clss_ipgre;
};

/* The PCI personality is not quite synonymous to protocol ID:
 * 1. All personalities need CORE connections
 * 2. The Ethernet personality may support also the RoCE protocol
@@ -430,6 +475,7 @@ struct qed_dev {
	u8				num_hwfns;
	struct qed_hwfn			hwfns[MAX_HWFNS_PER_DEVICE];

	unsigned long			tunn_mode;
	u32				drv_type;

	struct qed_eth_stats		*reset_stats;
+4 −2
Original line number Diff line number Diff line
@@ -558,6 +558,7 @@ static int qed_hw_init_port(struct qed_hwfn *p_hwfn,

static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
			  struct qed_ptt *p_ptt,
			  struct qed_tunn_start_params *p_tunn,
			  int hw_mode,
			  bool b_hw_start,
			  enum qed_int_mode int_mode,
@@ -625,7 +626,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
		qed_int_igu_enable(p_hwfn, p_ptt, int_mode);

		/* send function start command */
		rc = qed_sp_pf_start(p_hwfn, p_hwfn->cdev->mf_mode);
		rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode);
		if (rc)
			DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
	}
@@ -672,6 +673,7 @@ static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
}

int qed_hw_init(struct qed_dev *cdev,
		struct qed_tunn_start_params *p_tunn,
		bool b_hw_start,
		enum qed_int_mode int_mode,
		bool allow_npar_tx_switch,
@@ -724,7 +726,7 @@ int qed_hw_init(struct qed_dev *cdev,
		/* Fall into */
		case FW_MSG_CODE_DRV_LOAD_FUNCTION:
			rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
					    p_hwfn->hw_info.hw_mode,
					    p_tunn, p_hwfn->hw_info.hw_mode,
					    b_hw_start, int_mode,
					    allow_npar_tx_switch);
			break;
+2 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ void qed_resc_setup(struct qed_dev *cdev);
 * @brief qed_hw_init -
 *
 * @param cdev
 * @param p_tunn
 * @param b_hw_start
 * @param int_mode - interrupt mode [msix, inta, etc.] to use.
 * @param allow_npar_tx_switch - npar tx switching to be used
@@ -72,6 +73,7 @@ void qed_resc_setup(struct qed_dev *cdev);
 * @return int
 */
int qed_hw_init(struct qed_dev *cdev,
		struct qed_tunn_start_params *p_tunn,
		bool b_hw_start,
		enum qed_int_mode int_mode,
		bool allow_npar_tx_switch,
+50 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ enum common_ramrod_cmd_id {
	COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
	COMMON_RAMROD_RESERVED,
	COMMON_RAMROD_RESERVED2,
	COMMON_RAMROD_RESERVED3,
	COMMON_RAMROD_PF_UPDATE,
	COMMON_RAMROD_EMPTY,
	MAX_COMMON_RAMROD_CMD_ID
};
@@ -626,6 +626,42 @@ struct pf_start_ramrod_data {
	u8				reserved0[4];
};

/* tunnel configuration */
struct pf_update_tunnel_config {
	u8	update_rx_pf_clss;
	u8	update_tx_pf_clss;
	u8	set_vxlan_udp_port_flg;
	u8	set_geneve_udp_port_flg;
	u8	tx_enable_vxlan;
	u8	tx_enable_l2geneve;
	u8	tx_enable_ipgeneve;
	u8	tx_enable_l2gre;
	u8	tx_enable_ipgre;
	u8	tunnel_clss_vxlan;
	u8	tunnel_clss_l2geneve;
	u8	tunnel_clss_ipgeneve;
	u8	tunnel_clss_l2gre;
	u8	tunnel_clss_ipgre;
	__le16	vxlan_udp_port;
	__le16	geneve_udp_port;
	__le16	reserved[3];
};

struct pf_update_ramrod_data {
	u32				reserved[2];
	u32				reserved_1[6];
	struct pf_update_tunnel_config	tunnel_config;
};

/* Tunnel classification scheme */
enum tunnel_clss {
	TUNNEL_CLSS_MAC_VLAN = 0,
	TUNNEL_CLSS_MAC_VNI,
	TUNNEL_CLSS_INNER_MAC_VLAN,
	TUNNEL_CLSS_INNER_MAC_VNI,
	MAX_TUNNEL_CLSS
};

enum ports_mode {
	ENGX2_PORTX1 /* 2 engines x 1 port */,
	ENGX2_PORTX2 /* 2 engines x 2 ports */,
@@ -1603,6 +1639,19 @@ bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
			  u16			start_pq,
			  u16			num_pqs);

void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
			     struct qed_ptt  *p_ptt, u16 dest_port);
void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
			  struct qed_ptt *p_ptt, bool vxlan_enable);
void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
			struct qed_ptt  *p_ptt, bool eth_gre_enable,
			bool ip_gre_enable);
void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
			      struct qed_ptt *p_ptt, u16 dest_port);
void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
			   struct qed_ptt *p_ptt, bool eth_geneve_enable,
			   bool ip_geneve_enable);

/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
#define YSTORM_FLOW_CONTROL_MODE_OFFSET  (IRO[0].base)
#define YSTORM_FLOW_CONTROL_MODE_SIZE    (IRO[0].size)
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