Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 99336ed3 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/ltc: switch to device pri macros 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent d5c5bcf6

drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c

+29 −22
Original line number Diff line number Diff line
@@ -30,9 +30,10 @@ 
void

gf100_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit)

{

	nv_wr32(ltc, 0x17e8cc, start);

	nv_wr32(ltc, 0x17e8d0, limit);

	nv_wr32(ltc, 0x17e8c8, 0x00000004);

	struct nvkm_device *device = ltc->base.subdev.device;

	nvkm_wr32(device, 0x17e8cc, start);

	nvkm_wr32(device, 0x17e8d0, limit);

	nvkm_wr32(device, 0x17e8c8, 0x00000004);

}



void
@@ -48,18 +49,20 @@ gf100_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) 
void

gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4])

{

	nv_mask(ltc, 0x17ea44, 0x0000000f, i);

	nv_wr32(ltc, 0x17ea48, color[0]);

	nv_wr32(ltc, 0x17ea4c, color[1]);

	nv_wr32(ltc, 0x17ea50, color[2]);

	nv_wr32(ltc, 0x17ea54, color[3]);

	struct nvkm_device *device = ltc->base.subdev.device;

	nvkm_mask(device, 0x17ea44, 0x0000000f, i);

	nvkm_wr32(device, 0x17ea48, color[0]);

	nvkm_wr32(device, 0x17ea4c, color[1]);

	nvkm_wr32(device, 0x17ea50, color[2]);

	nvkm_wr32(device, 0x17ea54, color[3]);

}



void

gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth)

{

	nv_mask(ltc, 0x17ea44, 0x0000000f, i);

	nv_wr32(ltc, 0x17ea58, depth);

	struct nvkm_device *device = ltc->base.subdev.device;

	nvkm_mask(device, 0x17ea44, 0x0000000f, i);

	nvkm_wr32(device, 0x17ea58, depth);

}



static const struct nvkm_bitfield
@@ -83,8 +86,9 @@ gf100_ltc_lts_intr_name[] = { 
static void

gf100_ltc_lts_intr(struct nvkm_ltc_priv *ltc, int c, int s)

{

	struct nvkm_device *device = ltc->base.subdev.device;

	u32 base = 0x141000 + (c * 0x2000) + (s * 0x400);

	u32 intr = nv_rd32(ltc, base + 0x020);

	u32 intr = nvkm_rd32(device, base + 0x020);

	u32 stat = intr & 0x0000ffff;



	if (stat) {
@@ -93,16 +97,17 @@ gf100_ltc_lts_intr(struct nvkm_ltc_priv *ltc, int c, int s) 
		pr_cont("\n");

	}



	nv_wr32(ltc, base + 0x020, intr);

	nvkm_wr32(device, base + 0x020, intr);

}



void

gf100_ltc_intr(struct nvkm_subdev *subdev)

{

	struct nvkm_ltc_priv *ltc = (void *)subdev;

	struct nvkm_device *device = ltc->base.subdev.device;

	u32 mask;



	mask = nv_rd32(ltc, 0x00017c);

	mask = nvkm_rd32(device, 0x00017c);

	while (mask) {

		u32 s, c = __ffs(mask);

		for (s = 0; s < ltc->lts_nr; s++)
@@ -115,17 +120,18 @@ static int 
gf100_ltc_init(struct nvkm_object *object)

{

	struct nvkm_ltc_priv *ltc = (void *)object;

	u32 lpg128 = !(nv_rd32(ltc, 0x100c80) & 0x00000001);

	struct nvkm_device *device = ltc->base.subdev.device;

	u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);

	int ret;



	ret = nvkm_ltc_init(ltc);

	if (ret)

		return ret;



	nv_mask(ltc, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */

	nv_wr32(ltc, 0x17e8d8, ltc->ltc_nr);

	nv_wr32(ltc, 0x17e8d4, ltc->tag_base);

	nv_mask(ltc, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);

	nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */

	nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);

	nvkm_wr32(device, 0x17e8d4, ltc->tag_base);

	nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);

	return 0;

}
@@ -200,7 +206,8 @@ gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	       struct nvkm_oclass *oclass, void *data, u32 size,

	       struct nvkm_object **pobject)

{

	struct nvkm_fb *fb = nvkm_fb(parent);

	struct nvkm_device *device = (void *)parent;

	struct nvkm_fb *fb = device->fb;

	struct nvkm_ltc_priv *ltc;

	u32 parts, mask;

	int ret, i;
@@ -210,13 +217,13 @@ gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	if (ret)

		return ret;



	parts = nv_rd32(ltc, 0x022438);

	mask = nv_rd32(ltc, 0x022554);

	parts = nvkm_rd32(device, 0x022438);

	mask = nvkm_rd32(device, 0x022554);

	for (i = 0; i < parts; i++) {

		if (!(mask & (1 << i)))

			ltc->ltc_nr++;

	}

	ltc->lts_nr = nv_rd32(ltc, 0x17e8dc) >> 28;

	ltc->lts_nr = nvkm_rd32(device, 0x17e8dc) >> 28;



	ret = gf100_ltc_init_tag_ram(fb, ltc);

	if (ret)

drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c

+6 −5
Original line number Diff line number Diff line
@@ -27,17 +27,18 @@ static int 
gk104_ltc_init(struct nvkm_object *object)

{

	struct nvkm_ltc_priv *ltc = (void *)object;

	u32 lpg128 = !(nv_rd32(ltc, 0x100c80) & 0x00000001);

	struct nvkm_device *device = ltc->base.subdev.device;

	u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);

	int ret;



	ret = nvkm_ltc_init(ltc);

	if (ret)

		return ret;



	nv_wr32(ltc, 0x17e8d8, ltc->ltc_nr);

	nv_wr32(ltc, 0x17e000, ltc->ltc_nr);

	nv_wr32(ltc, 0x17e8d4, ltc->tag_base);

	nv_mask(ltc, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);

	nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);

	nvkm_wr32(device, 0x17e000, ltc->ltc_nr);

	nvkm_wr32(device, 0x17e8d4, ltc->tag_base);

	nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);

	return 0;

}

drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c

+28 −21
Original line number Diff line number Diff line
@@ -29,9 +29,10 @@ 
static void

gm107_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit)

{

	nv_wr32(ltc, 0x17e270, start);

	nv_wr32(ltc, 0x17e274, limit);

	nv_wr32(ltc, 0x17e26c, 0x00000004);

	struct nvkm_device *device = ltc->base.subdev.device;

	nvkm_wr32(device, 0x17e270, start);

	nvkm_wr32(device, 0x17e274, limit);

	nvkm_wr32(device, 0x17e26c, 0x00000004);

}



static void
@@ -47,29 +48,32 @@ gm107_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) 
static void

gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4])

{

	nv_mask(ltc, 0x17e338, 0x0000000f, i);

	nv_wr32(ltc, 0x17e33c, color[0]);

	nv_wr32(ltc, 0x17e340, color[1]);

	nv_wr32(ltc, 0x17e344, color[2]);

	nv_wr32(ltc, 0x17e348, color[3]);

	struct nvkm_device *device = ltc->base.subdev.device;

	nvkm_mask(device, 0x17e338, 0x0000000f, i);

	nvkm_wr32(device, 0x17e33c, color[0]);

	nvkm_wr32(device, 0x17e340, color[1]);

	nvkm_wr32(device, 0x17e344, color[2]);

	nvkm_wr32(device, 0x17e348, color[3]);

}



static void

gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth)

{

	nv_mask(ltc, 0x17e338, 0x0000000f, i);

	nv_wr32(ltc, 0x17e34c, depth);

	struct nvkm_device *device = ltc->base.subdev.device;

	nvkm_mask(device, 0x17e338, 0x0000000f, i);

	nvkm_wr32(device, 0x17e34c, depth);

}



static void

gm107_ltc_lts_isr(struct nvkm_ltc_priv *ltc, int c, int s)

{

	struct nvkm_device *device = ltc->base.subdev.device;

	u32 base = 0x140000 + (c * 0x2000) + (s * 0x400);

	u32 stat = nv_rd32(ltc, base + 0x00c);

	u32 stat = nvkm_rd32(device, base + 0x00c);



	if (stat) {

		nv_info(ltc, "LTC%d_LTS%d: 0x%08x\n", c, s, stat);

		nv_wr32(ltc, base + 0x00c, stat);

		nvkm_wr32(device, base + 0x00c, stat);

	}

}
@@ -77,9 +81,10 @@ static void 
gm107_ltc_intr(struct nvkm_subdev *subdev)

{

	struct nvkm_ltc_priv *ltc = (void *)subdev;

	struct nvkm_device *device = ltc->base.subdev.device;

	u32 mask;



	mask = nv_rd32(ltc, 0x00017c);

	mask = nvkm_rd32(device, 0x00017c);

	while (mask) {

		u32 s, c = __ffs(mask);

		for (s = 0; s < ltc->lts_nr; s++)
@@ -92,16 +97,17 @@ static int 
gm107_ltc_init(struct nvkm_object *object)

{

	struct nvkm_ltc_priv *ltc = (void *)object;

	u32 lpg128 = !(nv_rd32(ltc, 0x100c80) & 0x00000001);

	struct nvkm_device *device = ltc->base.subdev.device;

	u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);

	int ret;



	ret = nvkm_ltc_init(ltc);

	if (ret)

		return ret;



	nv_wr32(ltc, 0x17e27c, ltc->ltc_nr);

	nv_wr32(ltc, 0x17e278, ltc->tag_base);

	nv_mask(ltc, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);

	nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);

	nvkm_wr32(device, 0x17e278, ltc->tag_base);

	nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);

	return 0;

}
@@ -110,7 +116,8 @@ gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	       struct nvkm_oclass *oclass, void *data, u32 size,

	       struct nvkm_object **pobject)

{

	struct nvkm_fb *fb = nvkm_fb(parent);

	struct nvkm_device *device = (void *)parent;

	struct nvkm_fb *fb = device->fb;

	struct nvkm_ltc_priv *ltc;

	u32 parts, mask;

	int ret, i;
@@ -120,13 +127,13 @@ gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	if (ret)

		return ret;



	parts = nv_rd32(ltc, 0x022438);

	mask = nv_rd32(ltc, 0x021c14);

	parts = nvkm_rd32(device, 0x022438);

	mask = nvkm_rd32(device, 0x021c14);

	for (i = 0; i < parts; i++) {

		if (!(mask & (1 << i)))

			ltc->ltc_nr++;

	}

	ltc->lts_nr = nv_rd32(ltc, 0x17e280) >> 28;

	ltc->lts_nr = nvkm_rd32(device, 0x17e280) >> 28;



	ret = gf100_ltc_init_tag_ram(fb, ltc);

	if (ret)