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Commit 98fb7548 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Catalin Marinas
Browse files

arm64: update linker script to increased L1_CACHE_BYTES value 



Bring the linker script in line with the recent increase of
L1_CACHE_BYTES to 128. Replace the hardcoded value of 64 with the
symbolic constant.

Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
[catalin.marinas@arm.com: fix up RW_DATA_SECTION as well]
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 527e9316

arch/arm64/kernel/vmlinux.lds.S

+3 −2
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
 */



#include <asm-generic/vmlinux.lds.h>

#include <asm/cache.h>

#include <asm/kernel-pgtable.h>

#include <asm/thread_info.h>

#include <asm/memory.h>
@@ -140,7 +141,7 @@ SECTIONS 
		ARM_EXIT_KEEP(EXIT_DATA)

	}



	PERCPU_SECTION(64)

	PERCPU_SECTION(L1_CACHE_BYTES)



	. = ALIGN(PAGE_SIZE);

	__init_end = .;
@@ -158,7 +159,7 @@ SECTIONS 
	. = ALIGN(PAGE_SIZE);

	_data = .;

	_sdata = .;

	RW_DATA_SECTION(64, PAGE_SIZE, THREAD_SIZE)

	RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)

	PECOFF_EDATA_PADDING

	_edata = .;