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Commit 98c4b366 authored by Thierry Reding's avatar Thierry Reding
Browse files

clk: tegra: Add dpaux1 clock 



This clock is of the same type as dpaux and is added to feed into the
second DPAUX block used in conjunction with SOR1.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3d0f4e5f

drivers/clk/tegra/clk-id.h

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ enum clk_id { 
	tegra_clk_disp2_8,

	tegra_clk_dp2,

	tegra_clk_dpaux,

	tegra_clk_dpaux1,

	tegra_clk_dsialp,

	tegra_clk_dsia_mux,

	tegra_clk_dsiblp,

drivers/clk/tegra/clk-tegra-periph.c

+1 −0
Original line number Diff line number Diff line
@@ -822,6 +822,7 @@ static struct tegra_periph_init_data gate_clks[] = { 
	GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),

	GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),

	GATE("dpaux", "pll_p", 181, 0, tegra_clk_dpaux, 0),

	GATE("dpaux1", "pll_p", 207, 0, tegra_clk_dpaux1, 0),

	GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),

	GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),

	GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),

drivers/clk/tegra/clk-tegra210.c

+1 −0
Original line number Diff line number Diff line
@@ -2150,6 +2150,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },

	[tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },

	[tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },

	[tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },

	[tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },

	[tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },

	[tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },