pci-error-recovery: doc cleanup

Many PCI bus controllers are able to detect a variety of hardware

PCI errors on the bus, such as parity errors on the data and address

busses, as well as SERR and PERR errors.  Some of the more advanced

buses, as well as SERR and PERR errors.  Some of the more advanced

chipsets are able to deal with these errors; these include PCI-E chipsets,

and the PCI-host bridges found on IBM Power4, Power5 and Power6-based

pSeries boxes. A typical action taken is to disconnect the affected device,

STEP 3: Link Reset

------------------

The platform resets the link.  This is a PCI-Express specific step

and is done whenever a non-fatal error has been detected that can be

and is done whenever a fatal error has been detected that can be

"solved" by resetting the link.

STEP 4: Slot Reset

For most PCI devices, a soft reset will be sufficient for recovery.

Optional fundamental reset is provided to support a limited number

of PCI Express PCI devices  for which a soft reset is not sufficient

of PCI Express devices for which a soft reset is not sufficient

for recovery.

If the platform supports PCI hotplug, then the reset might be