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Commit 977da084 authored by vathsala nagaraju's avatar vathsala nagaraju Committed by Rodrigo Vivi
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drm/i915/psr: Set frames before SU entry for psr2 



Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.

v2 :
 - add macro  EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
 - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
 - add check ==1 for dpcd_read call (ville)

v3 : (Rodrigo)
 - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
 - replace with &=

v4 :
 - change the macro to shift value (jani)
 - updated register names

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarVathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1506419953-32605-2-git-send-email-vathsala.nagaraju@intel.com
parent ae59e633

drivers/gpu/drm/i915/i915_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -4055,7 +4055,7 @@ enum { 
#define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4

#define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)

#define   EDP_PSR2_IDLE_MASK		0xf

#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)

#define   EDP_PSR2_FRAME_BEFORE_SU(a)	((a)<<4)



#define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)

#define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)

drivers/gpu/drm/i915/intel_psr.c

+11 −2
Original line number Diff line number Diff line
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
	 */

	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);

	uint32_t val;

	uint8_t sink_latency;



	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
	 * mesh at all with our frontbuffer tracking. And the hw alone isn't

	 * good enough. */

	val |= EDP_PSR2_ENABLE |

		EDP_SU_TRACK_ENABLE |

		EDP_FRAMES_BEFORE_SU_ENTRY;

		EDP_SU_TRACK_ENABLE;



	if (drm_dp_dpcd_readb(&intel_dp->aux,

				DP_SYNCHRONIZATION_LATENCY_IN_SINK,

				&sink_latency) == 1) {

		sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK;

	} else {

		sink_latency = 0;

	}

	val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);



	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)

		val |= EDP_PSR2_TP2_TIME_2500;