clk: mediatek: Add initial common clock support for Mediatek SoCs. (9741b1a6) · Commits · e / devices / android_kernel_teracube_emerald

drivers/clk/Makefile

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		@@ -51,6 +51,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
		obj-$(CONFIG_ARCH_HIP04) += hisilicon/
		obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
		obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
		obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
		ifeq ($(CONFIG_COMMON_CLK), y)
		obj-$(CONFIG_ARCH_MMP) += mmp/
		endif

drivers/clk/mediatek/Makefile

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		obj-y += clk-mtk.o clk-pll.o clk-gate.o

drivers/clk/mediatek/clk-gate.c

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		/*
		* Copyright (c) 2014 MediaTek Inc.
		* Author: James Liao <jamesjj.liao@mediatek.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/of.h>
		#include <linux/of_address.h>

		#include <linux/io.h>
		#include <linux/slab.h>
		#include <linux/delay.h>
		#include <linux/clkdev.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
		{
		struct mtk_clk_gate *cg = to_clk_gate(hw);
		u32 val;

		regmap_read(cg->regmap, cg->sta_ofs, &val);

		val &= BIT(cg->bit);

		return val == 0;
		}

		static int mtk_cg_bit_is_set(struct clk_hw *hw)
		{
		struct mtk_clk_gate *cg = to_clk_gate(hw);
		u32 val;

		regmap_read(cg->regmap, cg->sta_ofs, &val);

		val &= BIT(cg->bit);

		return val != 0;
		}

		static void mtk_cg_set_bit(struct clk_hw *hw)
		{
		struct mtk_clk_gate *cg = to_clk_gate(hw);

		regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
		}

		static void mtk_cg_clr_bit(struct clk_hw *hw)
		{
		struct mtk_clk_gate *cg = to_clk_gate(hw);

		regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
		}

		static int mtk_cg_enable(struct clk_hw *hw)
		{
		mtk_cg_clr_bit(hw);

		return 0;
		}

		static void mtk_cg_disable(struct clk_hw *hw)
		{
		mtk_cg_set_bit(hw);
		}

		static int mtk_cg_enable_inv(struct clk_hw *hw)
		{
		mtk_cg_set_bit(hw);

		return 0;
		}

		static void mtk_cg_disable_inv(struct clk_hw *hw)
		{
		mtk_cg_clr_bit(hw);
		}

		const struct clk_ops mtk_clk_gate_ops_setclr = {
		.is_enabled = mtk_cg_bit_is_cleared,
		.enable = mtk_cg_enable,
		.disable = mtk_cg_disable,
		};

		const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
		.is_enabled = mtk_cg_bit_is_set,
		.enable = mtk_cg_enable_inv,
		.disable = mtk_cg_disable_inv,
		};

		struct clk *mtk_clk_register_gate(
		const char *name,
		const char *parent_name,
		struct regmap *regmap,
		int set_ofs,
		int clr_ofs,
		int sta_ofs,
		u8 bit,
		const struct clk_ops *ops)
		{
		struct mtk_clk_gate *cg;
		struct clk *clk;
		struct clk_init_data init;

		cg = kzalloc(sizeof(*cg), GFP_KERNEL);
		if (!cg)
		return ERR_PTR(-ENOMEM);

		init.name = name;
		init.flags = CLK_SET_RATE_PARENT;
		init.parent_names = parent_name ? &parent_name : NULL;
		init.num_parents = parent_name ? 1 : 0;
		init.ops = ops;

		cg->regmap = regmap;
		cg->set_ofs = set_ofs;
		cg->clr_ofs = clr_ofs;
		cg->sta_ofs = sta_ofs;
		cg->bit = bit;

		cg->hw.init = &init;

		clk = clk_register(NULL, &cg->hw);
		if (IS_ERR(clk))
		kfree(cg);

		return clk;
		}

drivers/clk/mediatek/clk-gate.h

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		/*
		* Copyright (c) 2014 MediaTek Inc.
		* Author: James Liao <jamesjj.liao@mediatek.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#ifndef __DRV_CLK_GATE_H
		#define __DRV_CLK_GATE_H

		#include <linux/regmap.h>
		#include <linux/clk.h>
		#include <linux/clk-provider.h>

		struct mtk_clk_gate {
		struct clk_hw hw;
		struct regmap *regmap;
		int set_ofs;
		int clr_ofs;
		int sta_ofs;
		u8 bit;
		};

		static inline struct mtk_clk_gate to_clk_gate(struct clk_hw hw)
		{
		return container_of(hw, struct mtk_clk_gate, hw);
		}

		extern const struct clk_ops mtk_clk_gate_ops_setclr;
		extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;

		struct clk *mtk_clk_register_gate(
		const char *name,
		const char *parent_name,
		struct regmap *regmap,
		int set_ofs,
		int clr_ofs,
		int sta_ofs,
		u8 bit,
		const struct clk_ops *ops);

		#endif /* __DRV_CLK_GATE_H */

drivers/clk/mediatek/clk-mtk.c

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		/*
		* Copyright (c) 2014 MediaTek Inc.
		* Author: James Liao <jamesjj.liao@mediatek.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <linux/of.h>
		#include <linux/of_address.h>
		#include <linux/err.h>
		#include <linux/io.h>
		#include <linux/slab.h>
		#include <linux/delay.h>
		#include <linux/clkdev.h>
		#include <linux/mfd/syscon.h>

		#include "clk-mtk.h"
		#include "clk-gate.h"

		struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
		{
		int i;
		struct clk_onecell_data *clk_data;

		clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
		if (!clk_data)
		return NULL;

		clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
		if (!clk_data->clks)
		goto err_out;

		clk_data->clk_num = clk_num;

		for (i = 0; i < clk_num; i++)
		clk_data->clks[i] = ERR_PTR(-ENOENT);

		return clk_data;
		err_out:
		kfree(clk_data);

		return NULL;
		}

		void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
		struct clk_onecell_data *clk_data)
		{
		int i;
		struct clk *clk;

		for (i = 0; i < num; i++) {
		const struct mtk_fixed_factor *ff = &clks[i];

		clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
		CLK_SET_RATE_PARENT, ff->mult, ff->div);

		if (IS_ERR(clk)) {
		pr_err("Failed to register clk %s: %ld\n",
		ff->name, PTR_ERR(clk));
		continue;
		}

		if (clk_data)
		clk_data->clks[ff->id] = clk;
		}
		}

		int mtk_clk_register_gates(struct device_node node, const struct mtk_gate clks,
		int num, struct clk_onecell_data *clk_data)
		{
		int i;
		struct clk *clk;
		struct regmap *regmap;

		if (!clk_data)
		return -ENOMEM;

		regmap = syscon_node_to_regmap(node);
		if (IS_ERR(regmap)) {
		pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
		PTR_ERR(regmap));
		return PTR_ERR(regmap);
		}

		for (i = 0; i < num; i++) {
		const struct mtk_gate *gate = &clks[i];

		clk = mtk_clk_register_gate(gate->name, gate->parent_name,
		regmap,
		gate->regs->set_ofs,
		gate->regs->clr_ofs,
		gate->regs->sta_ofs,
		gate->shift, gate->ops);

		if (IS_ERR(clk)) {
		pr_err("Failed to register clk %s: %ld\n",
		gate->name, PTR_ERR(clk));
		continue;
		}

		clk_data->clks[gate->id] = clk;
		}

		return 0;
		}

		struct clk mtk_clk_register_composite(const struct mtk_composite mc,
		void __iomem base, spinlock_t lock)
		{
		struct clk *clk;
		struct clk_mux *mux = NULL;
		struct clk_gate *gate = NULL;
		struct clk_divider *div = NULL;
		struct clk_hw mux_hw = NULL, gate_hw = NULL, *div_hw = NULL;
		const struct clk_ops mux_ops = NULL, gate_ops = NULL, *div_ops = NULL;
		const char * const *parent_names;
		const char *parent;
		int num_parents;
		int ret;

		if (mc->mux_shift >= 0) {
		mux = kzalloc(sizeof(*mux), GFP_KERNEL);
		if (!mux)
		return ERR_PTR(-ENOMEM);

		mux->reg = base + mc->mux_reg;
		mux->mask = BIT(mc->mux_width) - 1;
		mux->shift = mc->mux_shift;
		mux->lock = lock;

		mux_hw = &mux->hw;
		mux_ops = &clk_mux_ops;

		parent_names = mc->parent_names;
		num_parents = mc->num_parents;
		} else {
		parent = mc->parent;
		parent_names = &parent;
		num_parents = 1;
		}

		if (mc->gate_shift >= 0) {
		gate = kzalloc(sizeof(*gate), GFP_KERNEL);
		if (!gate) {
		ret = -ENOMEM;
		goto err_out;
		}

		gate->reg = base + mc->gate_reg;
		gate->bit_idx = mc->gate_shift;
		gate->flags = CLK_GATE_SET_TO_DISABLE;
		gate->lock = lock;

		gate_hw = &gate->hw;
		gate_ops = &clk_gate_ops;
		}

		if (mc->divider_shift >= 0) {
		div = kzalloc(sizeof(*div), GFP_KERNEL);
		if (!div) {
		ret = -ENOMEM;
		goto err_out;
		}

		div->reg = base + mc->divider_reg;
		div->shift = mc->divider_shift;
		div->width = mc->divider_width;
		div->lock = lock;

		div_hw = &div->hw;
		div_ops = &clk_divider_ops;
		}

		clk = clk_register_composite(NULL, mc->name, parent_names, num_parents,
		mux_hw, mux_ops,
		div_hw, div_ops,
		gate_hw, gate_ops,
		mc->flags);

		if (IS_ERR(clk)) {
		kfree(gate);
		kfree(mux);
		}

		return clk;
		err_out:
		kfree(mux);

		return ERR_PTR(ret);
		}

		void mtk_clk_register_composites(const struct mtk_composite *mcs,
		int num, void __iomem base, spinlock_t lock,
		struct clk_onecell_data *clk_data)
		{
		struct clk *clk;
		int i;

		for (i = 0; i < num; i++) {
		const struct mtk_composite *mc = &mcs[i];

		clk = mtk_clk_register_composite(mc, base, lock);

		if (IS_ERR(clk)) {
		pr_err("Failed to register clk %s: %ld\n",
		mc->name, PTR_ERR(clk));
		continue;
		}

		if (clk_data)
		clk_data->clks[mc->id] = clk;
		}
		}