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Commit 973020fd authored by Antoine Tenart's avatar Antoine Tenart Committed by Gregory CLEMENT
Browse files

arm64: marvell: dts: add crypto engine description for 7k/8k 



Add the description of the crypto engine hardware block for the Marvell
Armada 7k and Armada 8k processors; for both the CP110 slave and master.

Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 910b4c5c

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -228,6 +228,21 @@ 
				status = "disabled";

			};



			cpm_crypto: crypto@800000 {

				compatible = "inside-secure,safexcel-eip197";

				reg = <0x800000 0x200000>;

				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING

				| IRQ_TYPE_LEVEL_HIGH)>,

					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "mem", "ring0", "ring1",

				"ring2", "ring3", "eip";

				clocks = <&cpm_syscon0 1 26>;

				status = "disabled";

			};

		};



		cpm_pcie0: pcie@f2600000 {

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -217,6 +217,22 @@ 
				clocks = <&cps_syscon0 1 25>;

				status = "okay";

			};



			cps_crypto: crypto@800000 {

				compatible = "inside-secure,safexcel-eip197";

				reg = <0x800000 0x200000>;

				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING

				| IRQ_TYPE_LEVEL_HIGH)>,

					     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "mem", "ring0", "ring1",

						  "ring2", "ring3", "eip";

				clocks = <&cps_syscon0 1 26>;

				status = "disabled";

			};

		};



		cps_pcie0: pcie@f4600000 {