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Commit 95d2b4e9 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

omap2/3/4: Clean up defines for entry-macro.S 



Define the irq base the same way as for omap2 and omap3,
and start using get_irqnr_preamble.

Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 1cf9d079

arch/arm/mach-omap2/include/mach/entry-macro.S

+7 −8
Original line number Diff line number Diff line
@@ -19,6 +19,12 @@ 
#include <plat/omap34xx.h>

#include <plat/omap44xx.h>



#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)

#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)

#define OMAP4_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)

#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */

#define	ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */



		.macro	disable_fiq

		.endm
@@ -27,11 +33,6 @@ 


#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)



#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)

#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)

#define INTCPS_SIR_IRQ_OFFSET	0x0040		/* Active interrupt offset */

#define	ACTIVEIRQ_MASK		0x7f		/* Active interrupt bits */



		.pushsection .data

omap_irq_base:	.word	0

		.popsection
@@ -90,8 +91,6 @@ omap_irq_base: .word 0 


#ifdef CONFIG_ARCH_OMAP4



#define OMAP44XX_VA_GIC_CPU_BASE	OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)



		.macro  get_irqnr_preamble, base, tmp

		.endm
@@ -115,7 +114,7 @@ omap_irq_base: .word 0 
		 * valid range for an IRQ (30-1020 inclusive).

		 */

		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp

		ldr     \base, =OMAP44XX_VA_GIC_CPU_BASE

		ldr     \base, =OMAP4_IRQ_BASE

		ldr     \irqstat, [\base, #GIC_CPU_INTACK]



		ldr     \tmp, =1021