Loading Documentation/devicetree/bindings/arm/gic.txt +6 −0 Original line number Original line Diff line number Diff line Loading @@ -50,6 +50,11 @@ Optional regions, used when the GIC doesn't have banked registers. The offset is regions, used when the GIC doesn't have banked registers. The offset is cpu-offset * cpu-nr. cpu-offset * cpu-nr. - arm,routable-irqs : Total number of gic irq inputs which are not directly connected from the peripherals, but are routed dynamically by a crossbar/multiplexer preceding the GIC. The GIC irq input line is assigned dynamically when the corresponding peripheral's crossbar line is mapped. Example: Example: intc: interrupt-controller@fff11000 { intc: interrupt-controller@fff11000 { Loading @@ -57,6 +62,7 @@ Example: #interrupt-cells = <3>; #interrupt-cells = <3>; #address-cells = <1>; #address-cells = <1>; interrupt-controller; interrupt-controller; arm,routable-irqs = <160>; reg = <0xfff11000 0x1000>, reg = <0xfff11000 0x1000>, <0xfff10100 0x100>; <0xfff10100 0x100>; }; }; Loading Documentation/devicetree/bindings/arm/omap/crossbar.txt 0 → 100644 +27 −0 Original line number Original line Diff line number Diff line Some socs have a large number of interrupts requests to service the needs of its many peripherals and subsystems. All of the interrupt lines from the subsystems are not needed at the same time, so they have to be muxed to the irq-controller appropriately. In such places a interrupt controllers are preceded by an CROSSBAR that provides flexibility in muxing the device requests to the controller inputs. Required properties: - compatible : Should be "ti,irq-crossbar" - reg: Base address and the size of the crossbar registers. - ti,max-irqs: Total number of irqs available at the interrupt controller. - ti,reg-size: Size of a individual register in bytes. Every individual register is assumed to be of same size. Valid sizes are 1, 2, 4. - ti,irqs-reserved: List of the reserved irq lines that are not muxed using crossbar. These interrupt lines are reserved in the soc, so crossbar bar driver should not consider them as free lines. Examples: crossbar_mpu: @4a020000 { compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; ti,max-irqs = <160>; ti,reg-size = <2>; ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; }; arch/arm/mach-omap2/Kconfig +1 −0 Original line number Original line Diff line number Diff line Loading @@ -85,6 +85,7 @@ config SOC_DRA7XX select CPU_V7 select CPU_V7 select HAVE_SMP select HAVE_SMP select HAVE_ARM_ARCH_TIMER select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR config ARCH_OMAP2PLUS config ARCH_OMAP2PLUS bool bool Loading arch/arm/mach-omap2/omap-wakeupgen.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -138,7 +138,7 @@ static void wakeupgen_mask(struct irq_data *d) unsigned long flags; unsigned long flags; raw_spin_lock_irqsave(&wakeupgen_lock, flags); raw_spin_lock_irqsave(&wakeupgen_lock, flags); _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]); _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]); raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); } } Loading @@ -150,7 +150,7 @@ static void wakeupgen_unmask(struct irq_data *d) unsigned long flags; unsigned long flags; raw_spin_lock_irqsave(&wakeupgen_lock, flags); raw_spin_lock_irqsave(&wakeupgen_lock, flags); _wakeupgen_set(d->irq, irq_target_cpu[d->irq]); _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]); raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); } } Loading arch/arm/mach-omap2/omap4-common.c +4 −0 Original line number Original line Diff line number Diff line Loading @@ -22,6 +22,7 @@ #include <linux/of_platform.h> #include <linux/of_platform.h> #include <linux/export.h> #include <linux/export.h> #include <linux/irqchip/arm-gic.h> #include <linux/irqchip/arm-gic.h> #include <linux/irqchip/irq-crossbar.h> #include <linux/of_address.h> #include <linux/of_address.h> #include <linux/reboot.h> #include <linux/reboot.h> Loading Loading @@ -288,5 +289,8 @@ void __init omap_gic_of_init(void) skip_errata_init: skip_errata_init: omap_wakeupgen_init(); omap_wakeupgen_init(); #ifdef CONFIG_IRQ_CROSSBAR irqcrossbar_init(); #endif irqchip_init(); irqchip_init(); } } Loading
Documentation/devicetree/bindings/arm/gic.txt +6 −0 Original line number Original line Diff line number Diff line Loading @@ -50,6 +50,11 @@ Optional regions, used when the GIC doesn't have banked registers. The offset is regions, used when the GIC doesn't have banked registers. The offset is cpu-offset * cpu-nr. cpu-offset * cpu-nr. - arm,routable-irqs : Total number of gic irq inputs which are not directly connected from the peripherals, but are routed dynamically by a crossbar/multiplexer preceding the GIC. The GIC irq input line is assigned dynamically when the corresponding peripheral's crossbar line is mapped. Example: Example: intc: interrupt-controller@fff11000 { intc: interrupt-controller@fff11000 { Loading @@ -57,6 +62,7 @@ Example: #interrupt-cells = <3>; #interrupt-cells = <3>; #address-cells = <1>; #address-cells = <1>; interrupt-controller; interrupt-controller; arm,routable-irqs = <160>; reg = <0xfff11000 0x1000>, reg = <0xfff11000 0x1000>, <0xfff10100 0x100>; <0xfff10100 0x100>; }; }; Loading
Documentation/devicetree/bindings/arm/omap/crossbar.txt 0 → 100644 +27 −0 Original line number Original line Diff line number Diff line Some socs have a large number of interrupts requests to service the needs of its many peripherals and subsystems. All of the interrupt lines from the subsystems are not needed at the same time, so they have to be muxed to the irq-controller appropriately. In such places a interrupt controllers are preceded by an CROSSBAR that provides flexibility in muxing the device requests to the controller inputs. Required properties: - compatible : Should be "ti,irq-crossbar" - reg: Base address and the size of the crossbar registers. - ti,max-irqs: Total number of irqs available at the interrupt controller. - ti,reg-size: Size of a individual register in bytes. Every individual register is assumed to be of same size. Valid sizes are 1, 2, 4. - ti,irqs-reserved: List of the reserved irq lines that are not muxed using crossbar. These interrupt lines are reserved in the soc, so crossbar bar driver should not consider them as free lines. Examples: crossbar_mpu: @4a020000 { compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; ti,max-irqs = <160>; ti,reg-size = <2>; ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; };
arch/arm/mach-omap2/Kconfig +1 −0 Original line number Original line Diff line number Diff line Loading @@ -85,6 +85,7 @@ config SOC_DRA7XX select CPU_V7 select CPU_V7 select HAVE_SMP select HAVE_SMP select HAVE_ARM_ARCH_TIMER select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR config ARCH_OMAP2PLUS config ARCH_OMAP2PLUS bool bool Loading
arch/arm/mach-omap2/omap-wakeupgen.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -138,7 +138,7 @@ static void wakeupgen_mask(struct irq_data *d) unsigned long flags; unsigned long flags; raw_spin_lock_irqsave(&wakeupgen_lock, flags); raw_spin_lock_irqsave(&wakeupgen_lock, flags); _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]); _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]); raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); } } Loading @@ -150,7 +150,7 @@ static void wakeupgen_unmask(struct irq_data *d) unsigned long flags; unsigned long flags; raw_spin_lock_irqsave(&wakeupgen_lock, flags); raw_spin_lock_irqsave(&wakeupgen_lock, flags); _wakeupgen_set(d->irq, irq_target_cpu[d->irq]); _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]); raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); } } Loading
arch/arm/mach-omap2/omap4-common.c +4 −0 Original line number Original line Diff line number Diff line Loading @@ -22,6 +22,7 @@ #include <linux/of_platform.h> #include <linux/of_platform.h> #include <linux/export.h> #include <linux/export.h> #include <linux/irqchip/arm-gic.h> #include <linux/irqchip/arm-gic.h> #include <linux/irqchip/irq-crossbar.h> #include <linux/of_address.h> #include <linux/of_address.h> #include <linux/reboot.h> #include <linux/reboot.h> Loading Loading @@ -288,5 +289,8 @@ void __init omap_gic_of_init(void) skip_errata_init: skip_errata_init: omap_wakeupgen_init(); omap_wakeupgen_init(); #ifdef CONFIG_IRQ_CROSSBAR irqcrossbar_init(); #endif irqchip_init(); irqchip_init(); } }