Commit 9558d15d authored May 13, 2016 by Ville Syrjälä

drm/i915: Fix BXT min_pixclk after state readout

commit 4e5ca60f ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
tried to change BXT to use ilk_max_pixel_rate() to compute the
pipe pixel rate. I failed to notice that there was another place
in the state readout code that needs the same treatment. So let's
change that one too.

Should probably just change things to always compuyte the pipe pixel
rates, instead of just doing on platforms that can change cdclk
dynamically. But for now let's just move BXT fully over to the
side that uses ilk_pipe_pixel_rate().

Cc: Jani Nikula <jani.nikula@intel.com>
Fixes: 4e5ca60f ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-2-git-send-email-ville.syrjala@linux.intel.com

Reviewed-by: Imre Deak <imre.deak@intel.com>

parent 03d92e47

drivers/gpu/drm/i915/intel_display.c

+6 −8

Original line number	Diff line number	Diff line
		@@ -15128,18 +15128,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
		if (crtc_state->base.active) {
		dev_priv->active_crtcs \|= 1 << crtc->pipe;

		if (IS_BROADWELL(dev_priv)) {
		if (IS_BROXTON(dev_priv) \|\| IS_BROADWELL(dev_priv))
		pixclk = ilk_pipe_pixel_rate(crtc_state);

		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
		if (crtc_state->ips_enabled)
		pixclk = DIV_ROUND_UP(pixclk * 100, 95);
		} else if (IS_VALLEYVIEW(dev_priv) \|\|
		IS_CHERRYVIEW(dev_priv) \|\|
		IS_BROXTON(dev_priv))
		else if (IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv))
		pixclk = crtc_state->base.adjusted_mode.crtc_clock;
		else
		WARN_ON(dev_priv->display.modeset_calc_cdclk);

		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
		if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
		pixclk = DIV_ROUND_UP(pixclk * 100, 95);
		}

		dev_priv->min_pixclk[crtc->pipe] = pixclk;