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Commit 950b2aae authored by Tim Gore's avatar Tim Gore Committed by Tvrtko Ursulin
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drm/i915/gen9: add WaClearFlowControlGpgpuContextSave 



This allows writes to EU flow control registers. Together
with SIP code from the user-mode driver this resolves a
hang seen in some pre-emption scenarios. Note that this
patch is just the kernel mode part of this workaround.

v2. Oops, add FLOW_CONTROL_ENABLE macro to i915_reg.h.

Signed-off-by: default avatarTim Gore <tim.gore@intel.com>
Reviewed-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458144826-17269-1-git-send-email-tim.gore@intel.com
parent 26720ab9

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -7105,6 +7105,7 @@ enum skl_disp_power_wells { 
#define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1<<3)



#define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)

#define   FLOW_CONTROL_ENABLE		(1<<15)

#define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)

#define   STALL_DOP_GATING_DISABLE		(1<<5)

drivers/gpu/drm/i915/intel_ringbuffer.c

+2 −0
Original line number Diff line number Diff line
@@ -925,8 +925,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) 
	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |

		   ECOCHK_DIS_TLB);



	/* WaClearFlowControlGpgpuContextSave:skl,bxt */

	/* WaDisablePartialInstShootdown:skl,bxt */

	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

			  FLOW_CONTROL_ENABLE |

			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);



	/* Syncing dependencies between camera and graphics:skl,bxt */