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Commit 94312828 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Mark up clflushes as belonging to an unordered timeline 



2 clflushes on two different objects are not ordered, and so do not
belong to the same timeline (context). Either we use a unique context
for each, or we reserve a special global context to mean unordered.
Ideally, we would reserve 0 to mean unordered (DMA_FENCE_NO_CONTEXT) to
have the same semantics everywhere.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170503093924.5320-1-chris@chris-wilson.co.uk
parent 6b07b6d2

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -1513,6 +1513,8 @@ struct i915_gem_mm { 
	/** LRU list of objects with fence regs on them. */

	struct list_head fence_list;



	u64 unordered_timeline;



	/* the indicator for dispatch video commands on two BSD rings */

	atomic_t bsd_engine_dispatch_index;

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -4745,7 +4745,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv) 


	mutex_lock(&dev_priv->drm.struct_mutex);



	i915_gem_clflush_init(dev_priv);

	dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);



	if (!i915.enable_execlists) {

		dev_priv->gt.resume = intel_legacy_submission_resume;

drivers/gpu/drm/i915/i915_gem_clflush.c

+1 −7
Original line number Diff line number Diff line
@@ -27,7 +27,6 @@ 
#include "i915_gem_clflush.h"



static DEFINE_SPINLOCK(clflush_lock);

static u64 clflush_context;



struct clflush {

	struct dma_fence dma; /* Must be first for dma_fence_free() */
@@ -157,7 +156,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj, 
		dma_fence_init(&clflush->dma,

			       &i915_clflush_ops,

			       &clflush_lock,

			       clflush_context,

			       to_i915(obj->base.dev)->mm.unordered_timeline,

			       0);

		i915_sw_fence_init(&clflush->wait, i915_clflush_notify);
@@ -182,8 +181,3 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj, 
		GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);

	}

}
 


void i915_gem_clflush_init(struct drm_i915_private *i915)

{

	clflush_context = dma_fence_context_alloc(1);

}

drivers/gpu/drm/i915/i915_gem_clflush.h

+0 −1
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@ 
struct drm_i915_private;

struct drm_i915_gem_object;



void i915_gem_clflush_init(struct drm_i915_private *i915);

void i915_gem_clflush_object(struct drm_i915_gem_object *obj,

			     unsigned int flags);

#define I915_CLFLUSH_FORCE BIT(0)