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Commit 93d68b25 authored by Colin Xu's avatar Colin Xu Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Handle EDP_PSR_IMR and EDP_PSR_IIR for BXT. 



BXT supports EDP. However since GVT-g only simulate DP monitor
to guest and handles EDP_PSR_IMR and EDP_PSR_IIR as default MMIO
r/w. If guest r/w these IMR/IIR, GVT-g won't simulate the real
HW behavior and below warning is printed:
--------
Interrupt register 0x64838 is not zero: 0xffffffff
WARNING: CPU: 1 PID: 1 at drivers/gpu/drm/i915/i915_irq.c:161
gen3_assert_iir_is_zero+0x34/0xa0

Call Trace:
gen8_de_irq_postinstall+0xad/0x330
gen8_irq_postinstall+0x23/0x80
drm_irq_install+0xb5/0x130
i915_driver_load+0xafd/0xf70
--------
Since GVT-g won't simulate EDP to guest, always set EDP_PSR_IMR
and EDP_PSR_IIR IMR/IIR to 0.

Signed-off-by: default avatarColin Xu <colin.xu@intel.com>

Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent aa36ed6d

drivers/gpu/drm/i915/gvt/handlers.c

+10 −0
Original line number Diff line number Diff line
@@ -1584,6 +1584,13 @@ static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 
	return 0;

}



static int bxt_edp_psr_imr_iir_write(struct intel_vgpu *vgpu,

		unsigned int offset, void *p_data, unsigned int bytes)

{

	vgpu_vreg(vgpu, offset) = 0;

	return 0;

}



static int mmio_read_from_hw(struct intel_vgpu *vgpu,

		unsigned int offset, void *p_data, unsigned int bytes)

{
@@ -3182,6 +3189,9 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);

	MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);



	MMIO_DH(EDP_PSR_IMR, D_BXT, NULL, bxt_edp_psr_imr_iir_write);

	MMIO_DH(EDP_PSR_IIR, D_BXT, NULL, bxt_edp_psr_imr_iir_write);



	MMIO_D(RC6_CTX_BASE, D_BXT);



	MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);