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Commit 93a17c05 authored by Tang Yuantian's avatar Tang Yuantian Committed by Michael Turquette
Browse files

clk: ppc-corenet: rename driver to clk-qoriq 



Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.

Signed-off-by: default avatarTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
parent 57bfd7ee

Documentation/devicetree/bindings/clock/qoriq-clock.txt

+3 −2
Original line number Diff line number Diff line 
* Clock Block on Freescale CoreNet Platforms

* Clock Block on Freescale QorIQ Platforms



Freescale CoreNet chips take primary clocking input from the external

Freescale qoriq chips take primary clocking input from the external

SYSCLK signal. The SYSCLK input (frequency) is multiplied using

multiple phase locked loops (PLL) to create a variety of frequencies

which can then be passed to a variety of internal logic, including
@@ -29,6 +29,7 @@ Required properties: 
	* "fsl,t4240-clockgen"

	* "fsl,b4420-clockgen"

	* "fsl,b4860-clockgen"

	* "fsl,ls1021a-clockgen"

	Chassis clock strings include:

	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks

	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks

drivers/clk/Kconfig

+5 −5
Original line number Diff line number Diff line
@@ -101,12 +101,12 @@ config COMMON_CLK_AXI_CLKGEN 
	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx

	  FPGAs. It is commonly used in Analog Devices' reference designs.



config CLK_PPC_CORENET

	bool "Clock driver for PowerPC corenet platforms"

	depends on PPC_E500MC && OF

config CLK_QORIQ

	bool "Clock driver for Freescale QorIQ platforms"

	depends on (PPC_E500MC || ARM) && OF

	---help---

	  This adds the clock driver support for Freescale PowerPC corenet

	  platforms using common clock framework.

	  This adds the clock driver support for Freescale QorIQ platforms

	  using common clock framework.



config COMMON_CLK_XGENE

	bool "Clock driver for APM XGene SoC"

drivers/clk/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o 
obj-$(CONFIG_ARCH_NOMADIK)		+= clk-nomadik.o

obj-$(CONFIG_ARCH_NSPIRE)		+= clk-nspire.o

obj-$(CONFIG_COMMON_CLK_PALMAS)		+= clk-palmas.o

obj-$(CONFIG_CLK_PPC_CORENET)		+= clk-ppc-corenet.o

obj-$(CONFIG_CLK_QORIQ)			+= clk-qoriq.o

obj-$(CONFIG_COMMON_CLK_RK808)		+= clk-rk808.o

obj-$(CONFIG_COMMON_CLK_S2MPS11)	+= clk-s2mps11.o

obj-$(CONFIG_COMMON_CLK_SI5351)		+= clk-si5351.o

drivers/clk/clk-ppc-corenet.c→drivers/clk/clk-qoriq.c

+3 −3
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * clock driver for Freescale PowerPC corenet SoCs.

 * clock driver for Freescale QorIQ SoCs.

 */

#include <linux/clk-provider.h>

#include <linux/io.h>
@@ -166,7 +166,7 @@ static void __init core_pll_init(struct device_node *np) 


	base = of_iomap(np, 0);

	if (!base) {

		pr_err("clk-ppc: iomap error\n");

		pr_err("clk-qoriq: iomap error\n");

		return;

	}
@@ -260,7 +260,7 @@ static void __init sysclk_init(struct device_node *node) 
	u32 rate;



	if (!np) {

		pr_err("ppc-clk: could not get parent node\n");

		pr_err("qoriq-clk: could not get parent node\n");

		return;

	}

drivers/cpufreq/Kconfig.powerpc

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ config CPU_FREQ_MAPLE 
config PPC_CORENET_CPUFREQ

	tristate "CPU frequency scaling driver for Freescale E500MC SoCs"

	depends on PPC_E500MC && OF && COMMON_CLK

	select CLK_PPC_CORENET

	select CLK_QORIQ

	help

	  This adds the CPUFreq driver support for Freescale e500mc,

	  e5500 and e6500 series SoCs which are capable of changing