Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 938de232 authored by Shirish S's avatar Shirish S Committed by Greg Kroah-Hartman
Browse files

x86/MCE/AMD: Carve out the MC4_MISC thresholding quirk 



[ Upstream commit 30aa3d26edb0f3d7992757287eec0ca588a5c259 ]

The MC4_MISC thresholding quirk needs to be applied during S5 -> S0 and
S3 -> S0 state transitions, which follow different code paths. Carve it
out into a separate function and call it mce_amd_feature_init() where
the two code paths of the state transitions converge.

 [ bp: massage commit message and the carved out function. ]

Signed-off-by: default avatarShirish S <shirish.s@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1547651417-23583-3-git-send-email-shirish.s@amd.com


Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 805f5ff8

arch/x86/kernel/cpu/mcheck/mce.c

+0 −29
Original line number Diff line number Diff line
@@ -1631,35 +1631,6 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 
		if (c->x86 == 0x15 && c->x86_model <= 0xf)

			mce_flags.overflow_recov = 1;



		/*

		 * Turn off MC4_MISC thresholding banks on all models since

		 * they're not supported there.

		 */

		if (c->x86 == 0x15) {

			int i;

			u64 hwcr;

			bool need_toggle;

			u32 msrs[] = {

				0x00000413, /* MC4_MISC0 */

				0xc0000408, /* MC4_MISC1 */

			};



			rdmsrl(MSR_K7_HWCR, hwcr);



			/* McStatusWrEn has to be set */

			need_toggle = !(hwcr & BIT(18));



			if (need_toggle)

				wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));



			/* Clear CntP bit safely */

			for (i = 0; i < ARRAY_SIZE(msrs); i++)

				msr_clear_bit(msrs[i], 62);



			/* restore old settings */

			if (need_toggle)

				wrmsrl(MSR_K7_HWCR, hwcr);

		}

	}



	if (c->x86_vendor == X86_VENDOR_INTEL) {

arch/x86/kernel/cpu/mcheck/mce_amd.c

+36 −0
Original line number Diff line number Diff line
@@ -545,6 +545,40 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 
	return offset;

}



/*

 * Turn off MC4_MISC thresholding banks on all family 0x15 models since

 * they're not supported there.

 */

void disable_err_thresholding(struct cpuinfo_x86 *c)

{

	int i;

	u64 hwcr;

	bool need_toggle;

	u32 msrs[] = {

		0x00000413, /* MC4_MISC0 */

		0xc0000408, /* MC4_MISC1 */

	};



	if (c->x86 != 0x15)

		return;



	rdmsrl(MSR_K7_HWCR, hwcr);



	/* McStatusWrEn has to be set */

	need_toggle = !(hwcr & BIT(18));



	if (need_toggle)

		wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));



	/* Clear CntP bit safely */

	for (i = 0; i < ARRAY_SIZE(msrs); i++)

		msr_clear_bit(msrs[i], 62);



	/* restore old settings */

	if (need_toggle)

		wrmsrl(MSR_K7_HWCR, hwcr);

}



/* cpu init entry point, called from mce.c with preempt off */

void mce_amd_feature_init(struct cpuinfo_x86 *c)

{
@@ -552,6 +586,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) 
	unsigned int bank, block, cpu = smp_processor_id();

	int offset = -1;



	disable_err_thresholding(c);



	for (bank = 0; bank < mca_cfg.banks; ++bank) {

		if (mce_flags.smca)

			smca_configure(bank, cpu);